Lalit Sharma
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0ee3efb306
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Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |
tangxifan
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6b50bbf986
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Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
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2020-12-08 15:32:48 -07:00 |
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tangxifan
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6001da3a40
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[Arch] Bug fix in tileable I/O arch example
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2020-12-04 17:56:54 -07:00 |
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tangxifan
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1d0bdcfeca
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[Arch] Simplify the grid layout modeling
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2020-12-04 17:38:44 -07:00 |
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tangxifan
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1c3f625e41
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[Arch] Force empty tiles at corners for tileable I/O arch example
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2020-12-04 17:11:06 -07:00 |
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tangxifan
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0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
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186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
ganeshgore
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289d9d2169
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[Bugfix] Honors yosys_tmpl parameter in flow script
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2020-12-03 12:24:24 -07:00 |
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tangxifan
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412fb5bb31
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[Arch] Bug fix due to valid default value parser
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2020-12-02 17:51:50 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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c7604ab94f
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[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
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2020-11-30 18:02:00 -07:00 |
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tangxifan
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ff53d2c375
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[HDL] Add new Scan-chain DFF cell
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2020-11-30 17:54:10 -07:00 |
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tangxifan
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ad703ad85b
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[HDL] Add new gpio cell with protection circuitry
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2020-11-30 17:52:39 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
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7a0a3398d4
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[Arch] Add new architecture to test global reset ports defined thru tile ports
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2020-11-30 17:43:41 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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tangxifan
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a60bd4d14a
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[Arch] Bug fix in nature fracturable architecture
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2020-11-25 22:48:26 -07:00 |
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ganeshgore
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7db030018c
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[Bug] Fixed variable file location
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2020-11-25 22:44:40 -07:00 |
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tangxifan
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b8559249dc
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[Test] Bug fix in task configuration file
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2020-11-25 22:23:27 -07:00 |
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tangxifan
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26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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tangxifan
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17070c6405
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[Doc] Update README in openfpga arch directory for native fracturable LUT design
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2020-11-25 22:19:20 -07:00 |
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tangxifan
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f6a667de58
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[Arch] Add openfpga architecture using native fracturable LUT
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2020-11-25 22:18:03 -07:00 |
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tangxifan
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eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
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0f841aa6d1
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[Arch] Add an example architecture using native fracturable LUT
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2020-11-25 22:11:14 -07:00 |
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ganeshgore
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59bd7d0f18
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[Flow] Changed substitute to safe_sustitute option
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2020-11-25 22:09:36 -07:00 |
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ganeshgore
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fefba0db59
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Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
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2020-11-25 17:29:53 -07:00 |
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ganeshgore
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1d993296d8
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[Flow] Example of using test variable in task conf
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2020-11-25 17:25:12 -07:00 |
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ganeshgore
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1554f583b7
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[Flow] Now support explicit variable file for task
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2020-11-25 17:22:41 -07:00 |
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tangxifan
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fd80cacaa3
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[Flow] Add example script for behaviorial verilog generation
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2020-11-22 21:14:10 -07:00 |
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tangxifan
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617f7e3062
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[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |
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tangxifan
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5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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348872f8a4
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[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
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2020-11-22 16:12:28 -07:00 |
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tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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91b0dbbaa2
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[Script] Add example openfpga shell run script when using global tile clocks
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2020-11-17 14:33:12 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |
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tangxifan
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f29916921a
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[Arch] Add openfpga arch for using global clocks from tiles
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2020-11-10 19:20:08 -07:00 |
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tangxifan
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a6531d9e8d
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[Arch] Add k4 arch using global clock from tile port (with zero fc)
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2020-11-10 19:17:34 -07:00 |
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tangxifan
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75ce4b5e25
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[Arch] Fine tune example arch
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2020-11-10 14:38:47 -07:00 |
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tangxifan
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d127304760
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[Arch] Update sample arch using local clock from physical tile ports
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2020-11-10 14:31:58 -07:00 |
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tangxifan
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4ca2a129c2
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[Arch] Add an sample architecture where global clock port is defined from tile ports
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2020-11-10 11:47:03 -07:00 |
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tangxifan
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70734abc35
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[Arch] Remove QN from stdcell arch
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2020-11-06 11:20:13 -07:00 |
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tangxifan
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1a79a55646
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[HDL] Add DFF cell with reset but only 1 output
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2020-11-06 11:19:19 -07:00 |
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tangxifan
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2aab8bf910
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[Arch] Use single-output DFF for a standard cell FPGA
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2020-11-06 10:26:39 -07:00 |
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tangxifan
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7d46b35296
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[HDL] Add single-output DFF HDL
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2020-11-06 10:18:37 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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55f7a2c187
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Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
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2020-11-04 21:55:37 -07:00 |
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tangxifan
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bce8233019
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[Arch] Bug fix in caravel arch
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2020-11-04 20:58:58 -07:00 |
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tangxifan
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6b48ee7f0b
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[Test] Add new test for caravel io support
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2020-11-04 20:58:40 -07:00 |
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tangxifan
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c85edb4738
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[Arch] Bug fix for embedded io arch
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2020-11-04 20:52:47 -07:00 |
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tangxifan
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a6c7bb2c48
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[Arch] Update OpenFPGA arch for new syntax on I/O
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2020-11-04 20:24:02 -07:00 |