tangxifan
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ee6b1d6cd6
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adapt arch xml and act for demo
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2018-12-13 22:46:40 -07:00 |
AurelienUoU
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f5ea3ff233
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Add an autochecked configuration free testbench
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2018-12-11 14:44:13 -07:00 |
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AurelienUoU
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5e94b7093d
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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Aur??Lien ALACCHI
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0580d8243f
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Add Autochek testbench option
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2018-12-08 17:19:12 -07:00 |
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Aur??Lien ALACCHI
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44b7f7f3d4
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Correct sub_modules.v generation to include decoders.v when necessary
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2018-12-05 13:52:25 -07:00 |
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Aur??Lien ALACCHI
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dc4accedd9
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Add forgottent files + add parameter transmission from verilog_api.c
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2018-12-05 11:33:14 -07:00 |
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Aur??Lien ALACCHI
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9a8c7b391a
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Add process for modelsim script autogeneration
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2018-12-05 09:20:47 -07:00 |
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Aur??Lien ALACCHI
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8ac566ecc0
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
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tangxifan
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c67ba5f58a
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clean up codes
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2018-09-27 14:26:08 -06:00 |
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tangxifan
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d683134b12
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |