AurelienUoU
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0e820d38ea
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Speedup the install on travis
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2019-05-29 16:53:35 -06:00 |
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AurelienUoU
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46fa1197b0
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Test reading tech file
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2019-05-29 16:43:56 -06:00 |
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AurelienUoU
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74ee6bad7f
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Update spice path in architecture
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2019-05-29 10:08:58 -06:00 |
tangxifan
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5b15a746d3
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add num_driver_nodes to Switch Block XML writter
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2019-05-28 20:52:33 -06:00 |
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tangxifan
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5ed076dfb4
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fixed a critical bug in rotating
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2019-05-28 17:55:09 -06:00 |
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tangxifan
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9cc5518d5a
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keep adding segment information for SB XML outputter
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2019-05-28 15:59:55 -06:00 |
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tangxifan
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e7e18eb4c1
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Add more information in SB XML outputter
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2019-05-28 15:56:41 -06:00 |
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tangxifan
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ca402f87e5
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 15:19:48 -06:00 |
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tangxifan
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ca363da30c
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add options to specify output directory of SB XML
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2019-05-28 15:19:10 -06:00 |
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AurelienUoU
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4ef25a7550
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 15:03:40 -06:00 |
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AurelienUoU
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f934f6f0a3
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Debug step
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2019-05-28 15:01:16 -06:00 |
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tangxifan
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6b51b42ee7
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 14:53:44 -06:00 |
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tangxifan
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af91fca1e0
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add rr_blocks XML writer to help debugging Switch Block Rotation
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2019-05-28 14:52:44 -06:00 |
Baudouin Chauviere
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3da216f297
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correction Null issue for the flat model
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2019-05-28 14:15:24 -06:00 |
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AurelienUoU
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ffdcd4bb9c
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Path correction 2
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2019-05-28 11:59:09 -06:00 |
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tangxifan
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c75ffa858b
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 11:26:16 -06:00 |
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tangxifan
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6f30d3ad05
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support rotation on segment groups inside RRChan and improve rotatable mirror searching
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2019-05-28 11:25:16 -06:00 |
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AurelienUoU
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20f80a73e7
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Correct path to tech files
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2019-05-28 11:24:03 -06:00 |
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AurelienUoU
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e0717369e1
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Re-insert power option in regression test
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2019-05-28 09:48:03 -06:00 |
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tangxifan
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0f5666ea11
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fixed the bug in mirror node direction
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2019-05-27 21:58:21 -06:00 |
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tangxifan
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eece161d58
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keep debugging on Switch Block rotation
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2019-05-27 21:10:30 -06:00 |
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tangxifan
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5720217cfd
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Add copy constructor for RRChan, RRSwitchBlock etc.
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2019-05-27 15:44:34 -06:00 |
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tangxifan
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1bea9870fc
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developed new rotating methods for RRSwitchBlocks, debugging ongoing
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2019-05-26 23:35:30 -06:00 |
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tangxifan
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4b852afeac
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skip rotating mirror detection which is too time-consuming
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2019-05-25 23:41:46 -06:00 |
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tangxifan
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22e71f5847
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Add rotate one side of switch block functionality
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2019-05-25 22:48:07 -06:00 |
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tangxifan
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858a323228
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Add more support for rotating Switch Blocks
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2019-05-25 21:26:35 -06:00 |
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tangxifan
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2eab0b1c1c
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update unique_mirror search algorithm for Switch Blocks
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2019-05-25 19:54:15 -06:00 |
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tangxifan
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d3eae80e64
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implemented an native way in finding rotable Switch blocks
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2019-05-25 19:37:18 -06:00 |
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tangxifan
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ae0248fbc6
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debugging SwitchBlock rotating
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2019-05-24 23:10:30 -06:00 |
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tangxifan
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9adc2945c8
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add rotate functionality for RRSwitchBlock
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2019-05-24 21:40:16 -06:00 |
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tangxifan
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02b48d036d
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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tangxifan
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2c46da6888
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clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
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tangxifan
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27b996337a
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fixed a critical bug in Compact Verilog generation for SB/CBs
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2019-05-24 16:14:46 -06:00 |
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tangxifan
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1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
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tangxifan
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f27b88db8d
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Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
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tangxifan
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27c234711e
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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tangxifan
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924136e7a2
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Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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tangxifan
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994b90ae53
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updated report_timing for using RRSwitchBlock
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2019-05-24 14:25:51 -06:00 |
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tangxifan
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eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
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5de38f023c
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-23 21:53:16 -06:00 |
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tangxifan
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8f4f590ff9
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update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
|
AurelienUoU
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d3f0ab59c2
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Remove -power token until option is fixed
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2019-05-23 19:26:25 -06:00 |
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AurelienUoU
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3811c18953
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Correct syntax error in tokens of regression_fpga_flow.sh
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2019-05-23 18:33:47 -06:00 |
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AurelienUoU
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1018134726
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Update yosys to latest version + add simulation in fpga_flow
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2019-05-23 17:55:49 -06:00 |
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tangxifan
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ee1a24d4ba
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-23 17:38:35 -06:00 |
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tangxifan
|
ea8c36ce6e
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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AurelienUoU
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555570c15e
|
Update Yosys from version 0.7 to version 0.8
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2019-05-23 16:03:08 -06:00 |
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tangxifan
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ec70bcee99
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-22 22:05:46 -06:00 |
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tangxifan
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4aab93b729
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update class rr_switch_block and be ready for updating the downstream verilog generator
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2019-05-22 22:04:31 -06:00 |
|
AurelienUoU
|
2b04376209
|
Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
|
2019-05-22 13:44:48 -06:00 |