Baudouin Chauviere
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be25b6dd66
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-20 14:11:03 -06:00 |
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Baudouin Chauviere
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3bd6c40a10
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Report timing modified to have only one liners
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2019-06-20 14:10:39 -06:00 |
AurelienUoU
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a7502bb43b
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Avoid configuration bits for module wihch don't require them
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2019-06-20 09:40:41 -06:00 |
tangxifan
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e7f2bd3b7c
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-19 21:31:54 -06:00 |
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tangxifan
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2f15d2d13c
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keep developing tileable rr_graph, track2ipin and opin2track to go
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2019-06-19 21:30:16 -06:00 |
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AurelienUoU
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ff00e4c79c
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Free only if it's possible to free
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2019-06-19 16:15:30 -06:00 |
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tangxifan
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ba15358564
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developing ipin2track mapping for tiles
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2019-06-18 18:06:21 -06:00 |
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tangxifan
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9ca1b42f4c
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developing switch block pattern for tileable routing architecture
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2019-06-18 16:52:42 -06:00 |
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tangxifan
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352c97302b
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start building object GSB graph
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2019-06-17 22:10:30 -06:00 |
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tangxifan
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f4191315da
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use rr_gsb to build edges of rr_graph
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2019-06-17 18:01:45 -06:00 |
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tangxifan
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51ff150a77
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bug fixing in tileable rr_graph generator
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2019-06-17 10:16:08 -06:00 |
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tangxifan
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0d14fef53e
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bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
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2019-06-16 23:02:18 -06:00 |
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tangxifan
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04ffb99ca6
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-16 16:01:30 -06:00 |
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Baudouin Chauviere
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57a4ad1f99
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Break memories even in the clb sdc
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2019-06-16 14:27:29 -06:00 |
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tangxifan
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1af3b5ef55
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set chan_rr_nodes in tileable rr_graph builder
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2019-06-16 14:23:19 -06:00 |
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tangxifan
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8c9cc003ea
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developing routing track rr_node set up in tileable routing architecture
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2019-06-15 18:11:08 -06:00 |
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tangxifan
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28f54961b2
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Merge branch 'multimode_clb' into fpga_spice
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2019-06-15 15:37:26 -06:00 |
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Xifan Tang
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155c8d4924
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fix CMakeList bug in disabling VPR graphics
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2019-06-15 13:21:25 -06:00 |
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tangxifan
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18c355d3ee
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Merge branch 'multimode_clb' into tileable_routing
Conflicts:
vpr7_x2p/vpr/regression_verilog.sh
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2019-06-15 12:27:40 -06:00 |
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tangxifan
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b9feaf0eeb
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fix conflicts on the regression.sh
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2019-06-15 12:26:37 -06:00 |
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tangxifan
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d19b470b33
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Merge branch 'tileable_routing' into multimode_clb
Conflicts:
vpr7_x2p/vpr/regression_verilog.sh
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2019-06-15 12:25:30 -06:00 |
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tangxifan
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c8bf456097
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bug fixing for memory leaking in allocating pb_rr_graph and power estimation
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2019-06-15 12:23:36 -06:00 |
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tangxifan
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d3296d0975
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developing tileable rr_graph builder
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2019-06-14 22:35:42 -06:00 |
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tangxifan
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a33627606e
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developing tileable routing track arrangement
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2019-06-14 17:35:40 -06:00 |
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AurelienUoU
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29dadc51b4
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-14 11:46:02 -06:00 |
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AurelienUoU
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c76dbaac33
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Update regression test avoiding overwritting files
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2019-06-14 11:44:44 -06:00 |
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tangxifan
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4d2a3680be
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support bus explicit port mapping to standard cells (for BRAMs)
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2019-06-14 11:09:15 -06:00 |
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tangxifan
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0902d1e75a
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c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
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tangxifan
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5f61cd8876
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
Conflicts:
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
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2019-06-13 16:32:39 -06:00 |
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tangxifan
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af1628abfe
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use bus port for primitives in Verilog generator
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2019-06-13 16:26:58 -06:00 |
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tangxifan
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dddbbac85c
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merge from multimode_clb bug fixing
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2019-06-13 15:59:34 -06:00 |
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tangxifan
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e86874adca
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into fpga_spice
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2019-06-13 15:54:27 -06:00 |
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AurelienUoU
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15b4cc9ecb
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Error correction in memory generation for pb_types without modes
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2019-06-13 15:34:25 -06:00 |
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tangxifan
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43128ad3f0
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fix a bug in formal verification port for memory bank configuration circuits
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2019-06-13 15:33:13 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |
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tangxifan
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5ae4dec0af
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fix bugs in CMakeList on enable/disable VPR Graphics
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2019-06-12 22:48:00 -06:00 |
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tangxifan
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1d00e3665b
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start developing tileable_rr_graph_builder
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2019-06-11 16:50:40 -06:00 |
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tangxifan
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65b5454f3a
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start developing tileable_rr_graph_builder
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2019-06-11 16:49:10 -06:00 |
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tangxifan
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b359893852
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-11 14:41:36 -06:00 |
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AurelienUoU
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bf13c1f731
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Add a script to create a new file with correct path rather than overwrite the existing
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2019-06-11 14:28:58 -06:00 |
Ganesh Gore
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1da363f7f1
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Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev
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2019-06-11 11:59:54 -06:00 |
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tangxifan
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7245917b9c
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fix a bug for iopad SPICE generation
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2019-06-11 11:43:56 -06:00 |
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Ganesh Gore
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1093e341a8
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Added additional architecure files
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2019-06-11 11:26:44 -06:00 |
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tangxifan
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1776ae3ec8
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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tangxifan
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8e3ad675e0
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use sstream for rr_block verilog writer
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2019-06-10 16:23:35 -06:00 |
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tangxifan
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009e5244d3
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minor fix on the port direction of configuration peripherals for memory decoders
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2019-06-10 15:39:35 -06:00 |
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tangxifan
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f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
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tangxifan
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e4f70771a2
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updated SDC generator to embrace the RRGSB data structure
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2019-06-10 14:47:27 -06:00 |
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tangxifan
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8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
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e31407f693
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start cleaning up SDC generator with new RRGSB data structure
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2019-06-10 10:57:26 -06:00 |