tangxifan
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dbd93e429d
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now pro_blif.pl can accept customized clock name
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2020-08-19 09:43:44 -06:00 |
ganeshgore
|
747c062f86
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BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |
|
ganeshgore
|
45af056304
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TASK_NAME and TASK_DIR variables are avaialble in config file now
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2020-07-27 14:14:57 -06:00 |
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ganeshgore
|
0e46e0d857
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Updated task.conf format to have transparent shell variables
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2020-07-27 14:08:58 -06:00 |
|
ganeshgore
|
3b6cd885f3
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BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
tangxifan
|
4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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ganeshgore
|
41585436c8
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Added external_fabric_key_file key
|
2020-06-12 15:37:12 -06:00 |
|
ganeshgore
|
c1b73efa62
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Added support for simulation setting file in the task flow
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2020-06-10 23:12:30 -06:00 |
|
ganeshgore
|
a3103f6afe
|
BugFix : Relative path for refrence benchmark fixed
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2020-04-25 20:16:17 -06:00 |
|
ganeshgore
|
9d1b3d6865
|
Fixed modelsim include references
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2020-04-24 21:53:57 -06:00 |
|
ganeshgore
|
689c4a3e19
|
BugFix: The filename in the previous commit
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2020-04-15 12:44:22 -06:00 |
|
ganeshgore
|
7f37bf1441
|
Added formal verification support to fpga_flow script
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2020-04-15 12:24:51 -06:00 |
|
ganeshgore
|
f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
|
2020-04-11 16:45:22 -06:00 |
|
ganeshgore
|
8ea272dc2c
|
Patched the OpenFPGA shell execution bug
|
2020-04-08 21:28:14 -06:00 |
|
ganeshgore
|
583a4d8767
|
Fixed bug in openfpga_flow script
|
2020-04-08 12:04:08 -06:00 |
|
ganeshgore
|
ea4122a8a4
|
Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
|
ganeshgore
|
d1d3446568
|
backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
|
ganeshgore
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46bb5ef9d0
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Added disp option in openfpga_flow, Default is --nodisp
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2020-01-23 10:04:38 -07:00 |
|
ganeshgore
|
f0bed1244c
|
Added blif file folding before VPR run
|
2020-01-09 16:50:34 -07:00 |
|
ganeshgore
|
74b650e9e1
|
Added fpga_x2p_duplicate_grid_pin option
|
2019-12-30 12:25:28 -07:00 |
|
ganeshgore
|
d1e260f54f
|
Spice related option added
|
2019-12-30 12:16:04 -07:00 |
|
Ganesh Gore
|
6bb11918dc
|
Updated modelsim and collected result
|
2019-11-16 19:10:04 -07:00 |
|
Ganesh Gore
|
00ec36c1af
|
Added Modelsim error check in log
|
2019-11-16 13:18:13 -07:00 |
|
Ganesh Gore
|
373dbe0718
|
First draft for multithreaded Modelsim simulation
|
2019-11-16 01:06:09 -07:00 |
|
Ganesh Gore
|
f05aede868
|
Added task support for modelsim script
|
2019-11-15 23:23:15 -07:00 |
|
Ganesh Gore
|
f52eaef622
|
Updated flow script and skipped travis upload on failure test setup.
|
2019-11-15 14:35:15 -07:00 |
|
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
Ganesh Gore
|
a880802803
|
Bug Fix: Corrected read VPR stat filename
|
2019-11-01 20:51:05 -06:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
|
2019-11-01 18:20:40 -06:00 |
|
Ganesh Gore
|
81180939ca
|
Bug fix: Missing exit_if_fail flag in fpga_flow script
|
2019-10-31 09:56:57 -06:00 |
|
Ganesh Gore
|
c034b871bb
|
Made activity file independent of power option
|
2019-10-15 16:08:25 -06:00 |
|
Ganesh Gore
|
eaf8ecee86
|
added _vpr.txt subscript to vpr log files
|
2019-10-15 16:07:34 -06:00 |
|
Ganesh Gore
|
d269472daf
|
Updated formality python script
|
2019-09-27 14:00:57 -06:00 |
|
Ganesh Gore
|
50039a4b6e
|
Added remove run directory option
|
2019-09-21 23:35:56 -06:00 |
|
Ganesh Gore
|
cd5fd6ce6c
|
Added explicit checking to VVP execution
|
2019-09-18 12:14:26 -06:00 |
|
Ganesh Gore
|
169732ccc1
|
Added verbose option in VVP output
|
2019-09-17 22:09:37 -06:00 |
|
Ganesh Gore
|
678e3181ba
|
Made compact_routing_hierarchy options uncond
|
2019-09-16 21:22:13 -06:00 |
|
Ganesh Gore
|
81b9c5b266
|
Added flag for VVP exit code
|
2019-09-14 12:35:47 -06:00 |
|
Ganesh Gore
|
e5c99c8b12
|
Quick terminate on fail added
|
2019-09-13 23:56:38 -06:00 |
|
Ganesh Gore
|
bd9e57bc37
|
Added better task name
|
2019-09-13 23:30:42 -06:00 |
|
Ganesh Gore
|
a6e592247e
|
Replaced options exit_on fail and show_thread logs
|
2019-09-13 22:50:20 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
Ganesh Gore
|
bcbcd463fe
|
Added pending runs in log
|
2019-09-06 11:48:13 -04:00 |
|
Ganesh Gore
|
702a7683a8
|
Ensure strict exit of fpga_flow on error
|
2019-09-05 10:23:35 -06:00 |
|
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
ad4c688206
|
Added print for JobID to architecture mapping
|
2019-08-31 22:04:57 -06:00 |
|
Ganesh Gore
|
f4e99c150a
|
resolve missing variable bug
|
2019-08-31 21:55:32 -06:00 |
|
Ganesh Gore
|
3d4f7f66fd
|
Updated to run with python3
|
2019-08-31 21:42:31 -06:00 |