tangxifan
|
5d6a90d983
|
[engine] remove compile warnings
|
2022-08-22 20:59:50 -07:00 |
|
tangxifan
|
d5f56aada3
|
[lib] typo
|
2022-08-22 18:29:20 -07:00 |
|
tangxifan
|
903dd6cef6
|
[engine] remove warnings
|
2022-08-18 15:56:18 -07:00 |
|
tangxifan
|
2d05462219
|
[lib] remove warnings
|
2022-08-18 15:53:51 -07:00 |
|
tangxifan
|
2957b3aa7f
|
[lib] remove useless header files
|
2022-08-18 15:40:29 -07:00 |
|
tangxifan
|
a52597361b
|
[script] remove duplicated libraries in dependency list for some libopenfpga
|
2022-08-18 11:34:01 -07:00 |
|
tangxifan
|
e909f4fabe
|
[lib] rename libopenfpga to libs
|
2022-08-18 10:27:20 -07:00 |
|
tangxifan
|
075900a7c9
|
[engine] remove out-of-date codes due to the upgrades in VTR submodule
|
2022-08-16 13:56:08 -07:00 |
coolbreeze413
|
9fd8c02e13
|
header inclusions required for MinGW windows build
|
2022-06-29 07:03:38 +05:30 |
Manadher Kharroubi
|
73d9b40124
|
adding Tcl interface to vpr
|
2022-06-07 09:15:20 -07:00 |
Szymon Kulis
|
c4e033ac9b
|
Include limits in argparse.cpp
|
2021-11-28 07:57:31 +01:00 |
|
tangxifan
|
1d96974b99
|
[Tool] Patch to remove compiler warnings
|
2021-02-04 16:54:04 -07:00 |
|
tangxifan
|
2483154c34
|
[Tool] Patch disable_packing XML syntax to be consistent with VPR upstream
|
2021-02-04 16:28:32 -07:00 |
|
tangxifan
|
dd4f83a374
|
bug fixing to constant string to display interconnect names
|
2020-04-07 18:28:19 -06:00 |
|
tangxifan
|
13cd48c119
|
add support on packable/unpackable modes in VPR architecture
|
2020-04-06 16:07:49 -06:00 |
|
tangxifan
|
610c71671f
|
experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
|
2020-03-24 16:47:45 -06:00 |
|
tangxifan
|
708fda9606
|
fixed a bug in using tileable routing when directlist is enabled
|
2020-03-20 16:38:58 -06:00 |
|
tangxifan
|
a0b150f12e
|
adding micro architecture using adder chain
|
2020-03-20 14:18:59 -06:00 |
|
tangxifan
|
5be118d695
|
tileable rr_graph builder ready to debug
|
2020-03-06 16:18:45 -07:00 |
|
tangxifan
|
2d86a02358
|
refactored LUT bitstream generation to use vtr logic
|
2020-02-25 12:45:13 -07:00 |
|
tangxifan
|
5006a4395d
|
bring RRGraph object and writer online
|
2020-01-31 16:39:40 -07:00 |
|
tangxifan
|
9269d7106d
|
move rr_graph back to vpr because the reader and writer requires too much dependency on the core engine
|
2020-01-31 15:42:44 -07:00 |
|
tangxifan
|
fb0bcd7a48
|
create rr_graph library to enforce unit test on the new data structures as well as compare to legacy rr_node
|
2020-01-31 12:29:50 -07:00 |
|
tangxifan
|
75c3507acf
|
add verbose output option for openfpga linking architecture
|
2020-01-31 11:36:58 -07:00 |
|
tangxifan
|
8a7a4dc48e
|
add physical type annotation for interconnects and inference
|
2020-01-28 21:59:10 -07:00 |
|
tangxifan
|
5ecb771673
|
debugging the annotation to physical mode of pb_types
|
2020-01-27 17:43:22 -07:00 |
|
tangxifan
|
a6fbbce33e
|
start developing the openfpga arch binding to vpr
|
2020-01-27 15:31:12 -07:00 |
|
tangxifan
|
48ecb6e48b
|
immigrate XML parser for circuit_lib to library readarchopenfpga
|
2020-01-12 18:11:00 -07:00 |
|
tangxifan
|
2901a6eec5
|
add missing tatum file due to the folder name tags is in the git ignore list!!!
|
2020-01-03 23:13:49 -05:00 |
|
tangxifan
|
60cbcf9104
|
add missing tatum
|
2020-01-03 22:42:17 -05:00 |
|
tangxifan
|
7a96f866bb
|
remove tatum temporarily
|
2020-01-03 22:41:49 -05:00 |
|
tangxifan
|
f1bafffa87
|
add vpr8 libs and core engine for further integration
|
2020-01-03 16:14:42 -07:00 |
|
tangxifan
|
f70f387f9f
|
minor tuning on ini compilation
|
2019-11-01 20:51:49 -06:00 |
|
tangxifan
|
3669a47d3b
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
Ganesh Gore
|
a3e9b4aea9
|
Added mINI/lib - INI Read write to project
|
2019-09-27 13:58:48 -06:00 |
|
tangxifan
|
2c7d6e3de4
|
adding port parsers
|
2019-08-09 17:48:55 -06:00 |
|
tangxifan
|
ad8c33e1ba
|
complete the mutators
|
2019-08-08 11:33:11 -06:00 |
|
tangxifan
|
38962c4607
|
adding member functions for circuit library
|
2019-08-07 15:45:27 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |