tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
|
2019-06-10 15:29:44 -06:00 |
|
tangxifan
|
e4f70771a2
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
|
tangxifan
|
8a8f4153ce
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
tangxifan
|
e31407f693
|
start cleaning up SDC generator with new RRGSB data structure
|
2019-06-10 10:57:26 -06:00 |
|
tangxifan
|
17bc7fc296
|
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
|
2019-06-08 20:11:22 -06:00 |
|
tangxifan
|
3a7139ee65
|
Merge branch 'tileable_sb' into multimode_clb
|
2019-06-08 15:15:52 -06:00 |
|
Xifan Tang
|
61e359efc5
|
Enable an option to disable/enable graphics in VPR compilation
|
2019-06-08 15:08:17 -06:00 |
|
tangxifan
|
90696def6d
|
remove vpr Makefile
|
2019-06-07 23:44:39 -06:00 |
|
tangxifan
|
d737c4ff46
|
fix path in regression test! TODO: must keep a duplicated copy for template.xml
|
2019-06-07 23:31:42 -06:00 |
|
tangxifan
|
3ad4a33751
|
update travis to use gcc8 and disable graphics for vpr when compile in osx
|
2019-06-07 22:38:21 -06:00 |
|
tangxifan
|
e8d52121c6
|
try j16 for travis in linux
|
2019-06-07 22:32:47 -06:00 |
|
tangxifan
|
1b02428c04
|
change travis gcc and gxx setting
|
2019-06-07 22:25:55 -06:00 |
|
tangxifan
|
f5b6ee6adf
|
update travis configuration and clean up repository
|
2019-06-07 22:19:11 -06:00 |
|
tangxifan
|
1f228dd42b
|
Merge branch 'tileable_sb' into multimode_clb
|
2019-06-07 20:23:32 -06:00 |
|
tangxifan
|
8c5ec4572d
|
revert string to sprintf
|
2019-06-07 20:20:41 -06:00 |
|
tangxifan
|
a55c577a61
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-07 18:56:32 -06:00 |
|
tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
AurelienUoU
|
345a081eff
|
Correct error of target to rewrite file in regression test
|
2019-06-07 17:37:56 -06:00 |
|
tangxifan
|
44ce0e8834
|
update gsb unique module detection and fix formal verification port direction
|
2019-06-07 17:18:38 -06:00 |
|
tangxifan
|
24d53390d8
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
|
tangxifan
|
c9f810ceb6
|
update rr_gsb to build connection blocks
|
2019-06-07 11:01:55 -06:00 |
|
tangxifan
|
472aff5acb
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
|
tangxifan
|
ce9fc5696c
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
tangxifan
|
8c1e7b799f
|
fixed critical bugs in Connection Block Unique Module detection
|
2019-06-06 16:31:50 -06:00 |
|
tangxifan
|
4f543c510c
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-06 12:50:03 -06:00 |
|
tangxifan
|
873e4d989f
|
fine-tuning Verilog format and node addition to rr_blocks
|
2019-06-06 12:48:41 -06:00 |
|
AurelienUoU
|
182d49da45
|
Update regression test scripts
|
2019-06-06 11:47:51 -06:00 |
|
tangxifan
|
c2de0eefb1
|
fix redundant comma in SB Verilog module
|
2019-06-06 09:15:05 -06:00 |
|
tangxifan
|
b9e1b1afc4
|
fix a critical bug in num_reserved_sram_ports
|
2019-06-05 17:31:01 -06:00 |
|
tangxifan
|
aaf8d23971
|
fix critical bugs in routing submodules
|
2019-06-05 16:43:18 -06:00 |
|
tangxifan
|
01e075377d
|
fix typo in Verilog generation
|
2019-06-05 15:30:34 -06:00 |
|
tangxifan
|
21d0cb52bc
|
Merge remote-tracking branch 'origin' into tileable_sb
|
2019-06-05 13:31:49 -06:00 |
|
tangxifan
|
24ca3104b0
|
fix minor bugs in Switch Block submodules
|
2019-06-05 13:30:55 -06:00 |
|
tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
|
2019-06-05 12:56:05 -06:00 |
|
AurelienUoU
|
84fabbd43b
|
Fix sdc analysis bug related to virtual nodes + add the option in regression test
|
2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
|
d24488092d
|
Fix bug
|
2019-06-05 11:40:04 -06:00 |
|
tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
|
2019-06-04 17:47:40 -06:00 |
|
AurelienUoU
|
fcc10d8acf
|
Correct fpga_flow/arch/template files
|
2019-06-04 16:45:04 -06:00 |
|
AurelienUoU
|
a2f6ded2a2
|
Add path modification in file changing a keyword into OpenFPGA full path
|
2019-06-04 15:21:15 -06:00 |
|
tangxifan
|
98b82c17be
|
bug fixing for clear RRSwitchBlock
|
2019-06-04 14:02:49 -06:00 |
|
tangxifan
|
2c6780ab92
|
add side mirror detection for RRSwitchBlock
|
2019-06-04 13:01:22 -06:00 |
|
AurelienUoU
|
eb72cb201c
|
Use debug cmake build type to avoid building error
|
2019-06-03 15:34:26 -06:00 |
|
AurelienUoU
|
6974a4618f
|
Test gcc6 cmake3.13
|
2019-06-03 14:53:52 -06:00 |
|
AurelienUoU
|
f51aa41c23
|
Correct gcc instantiation
|
2019-06-03 14:13:22 -06:00 |
|
AurelienUoU
|
c87c349c75
|
Test gcc6/cmake3.5
|
2019-06-03 13:58:00 -06:00 |
|
AurelienUoU
|
f4b8c3cf25
|
Try another combination cmake/gcc
|
2019-06-03 13:45:34 -06:00 |
|
AurelienUoU
|
ab9834798a
|
Test if travis issue is the same as spotted on VM
|
2019-06-03 12:01:37 -06:00 |
|
AurelienUoU
|
8a5ff37262
|
Verify cmake version called to build
|
2019-06-03 11:16:39 -06:00 |
|
AurelienUoU
|
813470d459
|
Test Cmake fix
|
2019-06-03 10:31:44 -06:00 |
|
AurelienUoU
|
4523bd21e9
|
Update version of cmake causing trouble
|
2019-06-03 10:21:24 -06:00 |