tangxifan
|
1a6f096393
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[test] deploy the new test to fpga bitstream regression tests
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2022-09-21 15:54:52 -07:00 |
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tangxifan
|
d6f017535a
|
[test] a new test case to validate the lut+adder pair in repacker
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2022-09-21 15:53:59 -07:00 |
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tangxifan
|
7a867385d2
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[benchmark] add a new benchmark test the mapping of LUT + adder pairs
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2022-09-21 15:47:04 -07:00 |
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tangxifan
|
e0f632cc9c
|
[test] fixed a bug
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2022-09-20 20:29:34 -07:00 |
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tangxifan
|
645d8df7b9
|
[test] fixed a bug
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2022-09-20 20:09:41 -07:00 |
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tangxifan
|
9042fc2422
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[test] now reg test should show diff details when failed
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2022-09-20 19:32:34 -07:00 |
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tangxifan
|
b8f1520367
|
[test] fixed a bug
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2022-09-20 18:12:23 -07:00 |
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tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
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2022-09-20 18:10:52 -07:00 |
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tangxifan
|
5e23be19a5
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[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
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2022-09-20 18:07:31 -07:00 |
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tangxifan
|
1b0b50b928
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[test] update golden netlist
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2022-09-20 16:04:05 -07:00 |
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tangxifan
|
a137f7148c
|
[arch] fixed a bug
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2022-09-20 15:47:15 -07:00 |
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tangxifan
|
da157ed5de
|
[test] debugging git-diff
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2022-09-20 15:31:39 -07:00 |
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tangxifan
|
3f8106f12e
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[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
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2022-09-20 15:19:32 -07:00 |
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tangxifan
|
6a896a9845
|
[test] debugging
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2022-09-20 14:08:22 -07:00 |
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tangxifan
|
ecfdc4a83a
|
[test] debugging
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2022-09-20 13:51:32 -07:00 |
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tangxifan
|
bdcdc7d294
|
[test] Now git diff in basic regression tests should capture the changes on golden outputs
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2022-09-20 13:36:31 -07:00 |
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tangxifan
|
a8d7b6c2c4
|
[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
|
a2e22787c2
|
[test] deploy the new test cases to the basic regression tests
|
2022-09-16 10:31:15 -07:00 |
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tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
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2022-09-16 10:29:19 -07:00 |
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tangxifan
|
f2e13e5ea9
|
[arch] add more flexible layout to test I/O center features
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2022-09-16 10:00:08 -07:00 |
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tangxifan
|
ec38b3990f
|
[arch] update to check OpenFPGA I/O indexing
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2022-09-14 13:58:12 -07:00 |
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tangxifan
|
83c89ae1bf
|
[arch] add more corner case to test the custom I/O location feature
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2022-09-13 23:05:41 -07:00 |
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tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
|
a37e270f25
|
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
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2022-09-13 16:57:18 -07:00 |
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tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
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tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
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tangxifan
|
a3d070ac6f
|
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
|
2022-09-12 10:43:21 -07:00 |
|
tangxifan
|
314f5395b4
|
[benchmark] fixed a bug which causes yosys failed
|
2022-09-09 17:04:59 -07:00 |
|
tangxifan
|
91fe27ff66
|
[test] deploy new test to ci
|
2022-09-09 17:00:28 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
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2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
cc974a80f7
|
[arch] added a new architecture to test the local routing architecture where reset is on LUT
|
2022-09-09 16:48:10 -07:00 |
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tangxifan
|
7a38c7dd18
|
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
|
2022-09-09 16:42:55 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
419a3a1e46
|
[arch] fixed a bug
|
2022-09-08 16:53:52 -07:00 |
|
tangxifan
|
122a323668
|
[arch] fixed bugs
|
2022-09-08 16:50:33 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
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tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
b1fad0b4e5
|
[arch] add an example architecture to show the use extended syntax
|
2022-09-08 16:19:21 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
|
2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
|
2022-09-06 14:59:00 -07:00 |
|
tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
|
2022-09-06 14:04:23 -07:00 |
|
tangxifan
|
c48f750f86
|
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
|
2022-09-01 20:10:29 -07:00 |
|
tangxifan
|
51dc082bd4
|
[test] force a fixed routing chan W for no time stamp test case
|
2022-09-01 15:02:40 -07:00 |
|
tangxifan
|
d86eb04c5d
|
[test] now no timestamp test case covers gsb files
|
2022-09-01 14:03:51 -07:00 |
|
tangxifan
|
201bca8968
|
[test] typo
|
2022-08-30 08:59:20 -07:00 |
|
tangxifan
|
5f88b9a226
|
[test] typo
|
2022-08-29 22:41:15 -07:00 |
|
tangxifan
|
0b5bdcdbb1
|
[test] deploy new test to basic regression tests
|
2022-08-29 22:07:56 -07:00 |
|
tangxifan
|
069e2b00b1
|
[test] add more test cases to validate gsb options
|
2022-08-29 22:03:06 -07:00 |
|
tangxifan
|
6ce1d4804c
|
[test] deploy new test case to basic regression tests
|
2022-08-01 21:05:05 -07:00 |