[benchmark] add a new benchmark test the mapping of LUT + adder pairs

openfpga_flow/benchmarks/micro_benchmark/wire_adder/wire_adder.blif

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+# An artificial benchmark created to test the mapping of LUT + adder pairs
+
+.model wire_adder
+.inputs a
+.outputs b
+
+.names $false
+.names $true
+1
+
+.name a a_inv
+0 1
+
+.subckt adder a=$true b=$false cout=a_cout
+.subckt adder a=a_inv b=$true sumout=b
+
+.end
+
+.model adder a b cin cout sumout
+.blackbox
+.end

openfpga_flow/benchmarks/micro_benchmark/wire_adder/wire_adder.v

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+/////////////////////////////////////////
+//  Functionality: A wire but implemented by an adder
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module wire_adder(a, b);
+
+input wire a;
+output wire b;
+
+assign b = a;
+
+endmodule