Commit Graph

167 Commits

Author SHA1 Message Date
tangxifan 56cedf6c8b [test] added a new test case to validate the support on different wire segment distribution on X and Y 2023-08-22 11:20:14 -07:00
tangxifan 1b132fd667 [test] add a new testcase to validate the support on different routing channel width on X and Y 2023-08-22 11:06:12 -07:00
tangxifan 15a8d8a76a [test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation 2023-08-18 21:59:06 -07:00
tangxifan 5f6050d404 [test] add a new test to validate combo: group tile, tile annotation and subtile 2023-08-18 21:48:40 -07:00
tangxifan 5ac8919ce0 [test] add a new testcase to validate subtile with tile annotations 2023-08-18 21:37:15 -07:00
tangxifan e82e4f487e [test] add a new test to validate io subtile support 2023-08-18 11:13:34 -07:00
tangxifan 913c232556 [test] deploy new test to basic reg test 2023-08-17 14:54:24 -07:00
tangxifan 16f102f4c1 [test] deploy new tests to basic regression tests 2023-08-11 13:07:41 -07:00
tangxifan b7048d3dc8 [test] adding new tests to validate group config block 2023-08-03 22:30:41 -07:00
tangxifan 3d56bd0ff2 [test] deploy the new test to ci 2023-07-27 17:03:55 -07:00
tangxifan 46e58a56cb [test] added a new test case to validate clock network when using the tile modules 2023-07-27 16:39:48 -07:00
tangxifan e9f2adf3f9 [test] add a new testcase to validate carry chain connections when using tile modules 2023-07-27 16:06:43 -07:00
tangxifan 1ea8a33d4b [test] add a new testcase to validate global tile connections on tile modules 2023-07-27 15:57:38 -07:00
tangxifan a2848940df [test] add a new testcase to ease debugging 2023-07-26 22:32:03 -07:00
tangxifan 5685fbd5e8 [test] adding a new test case to validate the tile modules on 4x4 fabric 2023-07-26 22:17:39 -07:00
tangxifan 0db4ef62e8 [test] add a new test for tile-based fabric: using preconfig testbenches 2023-07-25 15:48:14 -07:00
tangxifan 82fe63297a [test] add a new test for top-left tile grouping 2023-07-19 11:22:36 -07:00
tangxifan 930d98f2af [test] deploy new tests 2023-07-08 21:52:16 -07:00
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
tangxifan 962ba67e36 [test] adding new tests to validate fpga core wrapper naming rules 2023-06-23 14:47:21 -07:00
tangxifan efc9bf9907 [test] added new test case to validate bitstream generation 2023-06-19 12:40:37 -07:00
tangxifan 97b089ae3c [test] added new testcases to validate fpga core wrapper 2023-06-18 21:01:37 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 812553e13d [test] adding more test cases 2023-05-25 20:17:23 -07:00
tangxifan df771cb33a [test] add a new testcase for subtile and deploy it to basic regression test 2023-05-03 15:41:29 +08:00
tangxifan f06248a1b0 [test] add a new testcase to validate the ccff v2 2023-04-24 14:55:22 +08:00
tangxifan 02e964b16f [test] add a new test case for ccffv2 2023-04-22 15:41:19 +08:00
tangxifan 087636cefa [test] deploy new test to regression tests 2023-04-20 15:06:47 +08:00
tangxifan 7d333b3669 [test] add a new test for clock network: validate full testbench is working 2023-04-20 10:36:08 +08:00
tangxifan 780dec6b1b [test] add a new test to validate the programmable clock arch 2023-02-28 21:46:57 -08:00
Ganesh Gore 4f6b8c0905 Updated regression tests 2023-02-11 22:11:06 -07:00
tangxifan 8174f53796 [test] deploy new test to fpga bitstream regression 2023-01-24 15:42:01 -08:00
tangxifan 95dd4fd535 [test] deploy new test to basic regression tests 2023-01-18 18:17:53 -08:00
tangxifan 5aa85d82e6 [test] deploy the new test to basic regression tests 2023-01-13 22:07:45 -08:00
tangxifan bbf83101be [test] deploy new test to ci 2023-01-11 17:11:28 -08:00
tangxifan 43cb498827 [test] deploy new tests to basic regression tests 2023-01-01 17:07:25 -08:00
tangxifan 93b020b0b3 [test] deploy new test to basic regression tests 2022-12-30 18:26:22 -08:00
tangxifan c33b9f1b9b [script] enable eval mode in tcl reg test 2022-12-02 12:07:27 -08:00
tangxifan 156fac9fec [ci] deploy tcl test to ci 2022-12-02 11:46:14 -08:00
tangxifan 97c72c73f1 [test] add a small test to validate tcl integration 2022-12-02 11:43:46 -08:00
tangxifan 609e096b1a [test] added a new test to validate explicit port direction in pin table support 2022-10-17 15:25:19 -07:00
tangxifan aa78981e37 [test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory 2022-10-17 11:18:21 -07:00
tangxifan 5cf315958d [test] deploy new test to basic regression tests 2022-10-13 11:17:34 -07:00
tangxifan 13c819bb28 [ci] deply new test to ci 2022-10-01 11:04:08 -07:00
tangxifan ce0fbe1765 [test] fixed a few bugs 2022-09-29 15:32:31 -07:00
tangxifan 36603f9772
Merge branch 'master' into vtr_upgrade 2022-09-20 21:08:06 -07:00
tangxifan e0f632cc9c [test] fixed a bug 2022-09-20 20:29:34 -07:00
tangxifan 645d8df7b9 [test] fixed a bug 2022-09-20 20:09:41 -07:00
tangxifan 9042fc2422 [test] now reg test should show diff details when failed 2022-09-20 19:32:34 -07:00
tangxifan da157ed5de [test] debugging git-diff 2022-09-20 15:31:39 -07:00