tangxifan
|
0b473e3454
|
[test] fixed the bug in single-mode lut testcase
|
2023-11-14 09:35:26 -08:00 |
|
tangxifan
|
d78f18d235
|
[test] add new testcase
|
2023-11-13 14:11:34 -08:00 |
|
tangxifan
|
8e875f3453
|
[test] add a new test case to validate the new feature
|
2023-11-02 21:08:36 -07:00 |
|
tangxifan
|
c6f33bcd7f
|
[test] add new tests to cover the new features
|
2023-10-06 18:41:57 -07:00 |
|
tangxifan
|
7d83fc914c
|
[core] ad a new test case
|
2023-10-06 18:31:54 -07:00 |
|
tangxifan
|
5aa206e616
|
[core] fixed some bugs
|
2023-09-25 22:27:24 -07:00 |
|
tangxifan
|
60b8c396dc
|
[test] add a new test
|
2023-09-25 21:25:21 -07:00 |
|
tangxifan
|
663c9c9fa1
|
[test] add a new test to validate the tile port merge feature
|
2023-09-25 18:34:34 -07:00 |
|
tangxifan
|
a1ed277a88
|
[test] typo
|
2023-09-23 15:12:02 -07:00 |
|
tangxifan
|
00e1a5df11
|
[test] fixed some bugs
|
2023-09-23 12:44:47 -07:00 |
|
tangxifan
|
195aa7a9a8
|
[test] developing new test to increase coverage on module renaming
|
2023-09-23 12:40:20 -07:00 |
|
tangxifan
|
f3279bd885
|
[test] now use 4x4 fabric to check the using index netlists
|
2023-09-20 22:49:47 -07:00 |
|
tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
|
2023-09-17 23:16:15 -07:00 |
|
tangxifan
|
3fd60a165d
|
[test] typo
|
2023-09-17 17:42:15 -07:00 |
|
tangxifan
|
11e976ec92
|
[test] add a new test to validate renaming on fpga top/core modules
|
2023-09-17 17:38:37 -07:00 |
|
tangxifan
|
0ef1e0bde5
|
[test] add a new test to validate renaming rules
|
2023-09-17 13:29:12 -07:00 |
|
tangxifan
|
559fa45d89
|
[test] add a new test to validate module renaming using index
|
2023-09-16 17:55:52 -07:00 |
|
tangxifan
|
1287097ce5
|
[test] update golden netlists
|
2023-09-06 22:51:38 -07:00 |
|
tangxifan
|
401f8098a6
|
[test] update golden copies
|
2023-09-06 17:35:03 -07:00 |
|
tangxifan
|
db0bb291c2
|
[test] update settings
|
2023-08-22 15:22:48 -07:00 |
|
tangxifan
|
56cedf6c8b
|
[test] added a new test case to validate the support on different wire segment distribution on X and Y
|
2023-08-22 11:20:14 -07:00 |
|
tangxifan
|
1b132fd667
|
[test] add a new testcase to validate the support on different routing channel width on X and Y
|
2023-08-22 11:06:12 -07:00 |
|
tangxifan
|
15a8d8a76a
|
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
|
2023-08-18 21:59:06 -07:00 |
|
tangxifan
|
5f6050d404
|
[test] add a new test to validate combo: group tile, tile annotation and subtile
|
2023-08-18 21:48:40 -07:00 |
|
tangxifan
|
5ac8919ce0
|
[test] add a new testcase to validate subtile with tile annotations
|
2023-08-18 21:37:15 -07:00 |
|
tangxifan
|
e82e4f487e
|
[test] add a new test to validate io subtile support
|
2023-08-18 11:13:34 -07:00 |
|
tangxifan
|
3ac3eb4624
|
[test] adding more flavor to the L shape
|
2023-08-17 15:08:27 -07:00 |
|
tangxifan
|
85bc890009
|
[test] add a new test to validate comb options of group tile, group config block and L shape fabric
|
2023-08-17 14:52:30 -07:00 |
|
tangxifan
|
2f49c25f09
|
[test] updated
|
2023-08-11 21:19:06 -07:00 |
|
tangxifan
|
b155e660ee
|
[test] fixed a bug
|
2023-08-11 16:55:35 -07:00 |
|
tangxifan
|
253d5fa26c
|
[core] a new test to validate the L shape in homo geneous fpga
|
2023-08-11 13:05:46 -07:00 |
|
tangxifan
|
dc0eec8b81
|
[test] added a new test to validate L shapre
|
2023-08-11 12:49:38 -07:00 |
|
tangxifan
|
0e9cf6e909
|
[test] added a new testcase to validate heterogeneous fpga using group config block
|
2023-08-06 22:11:38 -07:00 |
|
tangxifan
|
3e33f262bc
|
[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
|
2023-08-06 18:59:24 -07:00 |
|
tangxifan
|
46b1de08c6
|
[test] fixed a bug
|
2023-08-05 22:07:46 -07:00 |
|
tangxifan
|
b7048d3dc8
|
[test] adding new tests to validate group config block
|
2023-08-03 22:30:41 -07:00 |
|
tangxifan
|
667c5f8944
|
[test] fixed a bug on the testcase
|
2023-07-27 22:02:28 -07:00 |
|
tangxifan
|
952e84fce1
|
[test] now heterogeneous testcases for tile modules pass
|
2023-07-27 20:30:32 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
65995d7c13
|
[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
|
2023-07-27 17:03:02 -07:00 |
|
tangxifan
|
46e58a56cb
|
[test] added a new test case to validate clock network when using the tile modules
|
2023-07-27 16:39:48 -07:00 |
|
tangxifan
|
81d699a723
|
[test] added a new testcase to validate carry chain connections in tile modules
|
2023-07-27 16:18:30 -07:00 |
|
tangxifan
|
e9f2adf3f9
|
[test] add a new testcase to validate carry chain connections when using tile modules
|
2023-07-27 16:06:43 -07:00 |
|
tangxifan
|
1ea8a33d4b
|
[test] add a new testcase to validate global tile connections on tile modules
|
2023-07-27 15:57:38 -07:00 |
|
tangxifan
|
a2848940df
|
[test] add a new testcase to ease debugging
|
2023-07-26 22:32:03 -07:00 |
|
tangxifan
|
5685fbd5e8
|
[test] adding a new test case to validate the tile modules on 4x4 fabric
|
2023-07-26 22:17:39 -07:00 |
|
tangxifan
|
bb837f4f79
|
[test] update golden netlists
|
2023-07-25 23:39:59 -07:00 |
|
tangxifan
|
0db4ef62e8
|
[test] add a new test for tile-based fabric: using preconfig testbenches
|
2023-07-25 15:48:14 -07:00 |
|
tangxifan
|
82fe63297a
|
[test] add a new test for top-left tile grouping
|
2023-07-19 11:22:36 -07:00 |
|
tangxifan
|
930d98f2af
|
[test] deploy new tests
|
2023-07-08 21:52:16 -07:00 |