tangxifan
|
0eebdaf942
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add grid port naming function for modules
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2019-12-24 15:07:03 -07:00 |
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tangxifan
|
43e78585ba
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add routing track naming function for unique modules
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2019-12-24 14:55:17 -07:00 |
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tangxifan
|
a36cb676c2
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minor fix in ctags to include library source files
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2019-12-18 22:24:58 +08:00 |
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tangxifan
|
a04631305c
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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tangxifan
|
73386dd1a9
|
refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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tangxifan
|
a176c253ee
|
remove legacy codes in FPGA-Verilog: routing block generation
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2019-12-04 16:15:50 -07:00 |
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tangxifan
|
95ea513339
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move refactored Verilog routing block generation functions to cpp files
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2019-12-04 16:09:27 -07:00 |
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tangxifan
|
322228de43
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remove legacy codes in FPGA-Verilog
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2019-12-04 16:02:43 -07:00 |
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tangxifan
|
0dd72999d5
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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tangxifan
|
0daf170e45
|
refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
|
tangxifan
|
13f964ea72
|
add bitstream file format introduction
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2019-12-04 13:41:31 -07:00 |
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tangxifan
|
40bddd4ed7
|
add FPL'19 paper to documentation reference
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2019-12-04 12:05:30 -07:00 |
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tangxifan
|
323c4fdc9a
|
clean up documentation build warnings and add guidelines for port naming
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2019-12-04 11:59:10 -07:00 |
AurelienUoU
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09fd2afa9c
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
|
AurelienUoU
|
32176eb352
|
Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
|
AurelienUoU
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4b4b38d4e8
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Update openfpga.sh to allow run-flow and simulation at the same time
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2019-12-03 14:07:10 -07:00 |
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AurelienUoU
|
2f14716f13
|
Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
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tangxifan
|
099863a956
|
make FPGA-X2P to be run conditionally
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2019-12-03 13:50:39 -07:00 |
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tangxifan
|
5b4ddfb3ce
|
use adapt yosys Makefile for OpenFPGA framework
|
2019-11-27 14:42:47 -07:00 |
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tangxifan
|
1c7fdac3f2
|
add CMakefile for yosys
|
2019-11-27 14:42:18 -07:00 |
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tangxifan
|
4d62dc1c3e
|
Upgrade to yosys-0.9
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2019-11-27 14:40:39 -07:00 |
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tangxifan
|
8cc72536d1
|
minor bug fixing
|
2019-11-22 15:54:14 -07:00 |
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tangxifan
|
96733f9ea8
|
add minor comments in task file for modelsim regression tests
|
2019-11-16 22:34:03 -07:00 |
Ganesh Gore
|
e6d14c8bf5
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 19:20:51 -07:00 |
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Ganesh Gore
|
3f235a16f9
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-16 19:14:34 -07:00 |
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Ganesh Gore
|
6bb11918dc
|
Updated modelsim and collected result
|
2019-11-16 19:10:04 -07:00 |
|
tangxifan
|
a13f406918
|
tweaking mcnc_big20 task run for modelsim
|
2019-11-16 18:00:55 -07:00 |
|
Ganesh Gore
|
3c2055156a
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 16:12:30 -07:00 |
|
Ganesh Gore
|
bfb03af2c8
|
Added run-task and run-flow functions
|
2019-11-16 15:52:32 -07:00 |
|
Ganesh Gore
|
cb1c7a8030
|
Added OpenFPGA bash function utility
|
2019-11-16 13:19:00 -07:00 |
|
Ganesh Gore
|
00ec36c1af
|
Added Modelsim error check in log
|
2019-11-16 13:18:13 -07:00 |
|
Ganesh Gore
|
373dbe0718
|
First draft for multithreaded Modelsim simulation
|
2019-11-16 01:06:09 -07:00 |
|
Ganesh Gore
|
f05aede868
|
Added task support for modelsim script
|
2019-11-15 23:23:15 -07:00 |
|
Ganesh Gore
|
1c4acff79b
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-15 14:54:13 -07:00 |
|
Ganesh Gore
|
f52eaef622
|
Updated flow script and skipped travis upload on failure test setup.
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2019-11-15 14:35:15 -07:00 |
|
Ganesh Gore
|
333d10c94c
|
Added vpr_fpga_verilog_print_simulation_ini option
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2019-11-15 14:26:57 -07:00 |
|
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
tangxifan
|
0c2ad5ab5e
|
critical bug fixed for some corner cases
|
2019-11-13 20:45:41 -07:00 |
|
tangxifan
|
1291b99d66
|
now make ini file generation more flexible: user can specify a name or use the default name
|
2019-11-13 12:55:57 -07:00 |
|
tangxifan
|
d84cd66287
|
refactored analysis SDC generator for grids
|
2019-11-12 22:18:13 -07:00 |
|
tangxifan
|
6c58a4dd92
|
refactored unused grid block SDC analysis generation
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2019-11-12 10:01:17 -07:00 |
|
tangxifan
|
8a57a29d2d
|
refactoring analysis SDC generation for grids
|
2019-11-11 22:38:11 -07:00 |
|
tangxifan
|
5f219b428c
|
refactored analysis SDC generation for switch blocks
|
2019-11-11 19:24:39 -07:00 |
|
tangxifan
|
876733f052
|
now we use module manager to generate analysis SDC, being independent from VPR structures
|
2019-11-10 21:15:34 -07:00 |
|
tangxifan
|
a849522be9
|
refactored CB SDC analysis generation
|
2019-11-10 20:15:16 -07:00 |
|
tangxifan
|
8e8e59b0ca
|
give specific name to mux so that we can bind it to SDC generator
|
2019-11-10 19:42:30 -07:00 |
|
tangxifan
|
3d711823e5
|
refactoring SDC generator for unused CBs
|
2019-11-10 18:15:13 -07:00 |
|
tangxifan
|
67b3b25bea
|
refactoring analysis sdc generation
|
2019-11-10 16:08:49 -07:00 |
|
tangxifan
|
1f368abfbe
|
refactoring analysis SDC generation
|
2019-11-10 15:40:54 -07:00 |
|
tangxifan
|
bcd8237263
|
refactored grid PnR SDC generator
|
2019-11-09 20:57:54 -07:00 |