tangxifan
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e9ee039e60
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Merge branch 'master' into rst_on_lut_strong
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2022-10-13 16:01:57 -07:00 |
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tangxifan
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33e2b16cb1
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[arch] fixed a bug which caused verification failed
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2022-10-13 15:33:43 -07:00 |
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tangxifan
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1c36ac28f1
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[arch] code format
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2022-10-13 12:17:32 -07:00 |
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tangxifan
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7b7217d116
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[arch]add new arch to test
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2022-10-13 11:08:51 -07:00 |
mustafa.arslan
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d7a253408d
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Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
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2022-10-13 14:00:59 +03:00 |
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mustafa.arslan
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6f55371d4b
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Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
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2022-10-13 13:53:32 +03:00 |
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tangxifan
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35869b480a
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Merge branch 'master' into xmllint
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2022-10-07 10:47:43 -07:00 |
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tangxifan
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85089cbc88
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[arch] apply xml format for all the architecture files
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2022-10-07 10:31:51 -07:00 |
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mustafa.arslan
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508c01cef6
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Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
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2022-10-07 09:38:07 +03:00 |
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tangxifan
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78f30cf072
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[test] add a new test to track the golden netlists where cout is not in GSB
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2022-09-30 15:38:27 -07:00 |
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tangxifan
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0d8d8446ee
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[test] fixed a bug where OPIN for direct connection is included in GSB
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2022-09-30 15:24:51 -07:00 |
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tangxifan
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b8f1520367
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[test] fixed a bug
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2022-09-20 18:12:23 -07:00 |
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tangxifan
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5e23be19a5
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[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
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2022-09-20 18:07:31 -07:00 |
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tangxifan
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7ed1548c6e
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[arch] fixed a few bugs
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2022-05-09 17:22:48 +08:00 |
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tangxifan
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812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
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c8da85cc24
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[Doc] Update naming convention for OpenFPGA architecture files
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2022-03-20 10:51:55 +08:00 |
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tangxifan
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a1e2d9c864
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[Arch] Add a new example openfpga arch where clock ports are independent
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2022-03-20 10:50:31 +08:00 |
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tangxifan
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9f7a182433
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[Arch] Typo
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2022-02-24 09:51:26 -08:00 |
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tangxifan
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fdaf97e60d
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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tangxifan
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e443a4567d
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[Arch] Typo
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2022-02-23 22:09:26 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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62b4a0b7ff
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[Flow] Add openfpga arch for DSP with registers
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2022-01-02 19:59:33 -08:00 |
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tangxifan
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7598455497
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[Doc] Update naming convention for architecture files
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2022-01-02 19:51:09 -08:00 |
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tangxifan
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b8d5920529
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-28 15:45:58 -07:00 |
Aram Kostanyan
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2eef21a1af
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Fixed port names for mult_36x36
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2021-10-26 19:14:43 +05:00 |
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tangxifan
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82e77b42c5
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[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
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2021-10-09 20:43:55 -07:00 |
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tangxifan
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d2859ca1c8
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[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
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2021-10-05 10:56:20 -07:00 |
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tangxifan
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fbef22b494
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[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
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2021-10-04 16:39:53 -07:00 |
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tangxifan
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86e7c963f8
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[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
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2021-10-02 22:19:20 -07:00 |
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tangxifan
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7ba5d27ea7
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[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
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2021-10-01 17:02:35 -07:00 |
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tangxifan
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fa57117f50
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[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
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2021-10-01 10:19:51 -07:00 |
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tangxifan
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41cc375746
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[Arch] define default CCFF model in ql bank example architecture that uses shift registers
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2021-09-29 16:34:40 -07:00 |
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tangxifan
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4968f0d11f
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Merge branch 'master' into qlbank_sr
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2021-09-28 14:20:30 -07:00 |
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tangxifan
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80232fc459
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[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
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2021-09-28 12:36:36 -07:00 |
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tangxifan
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4c04c0fbd7
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[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
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2021-09-28 12:35:42 -07:00 |
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tangxifan
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4aed045cdd
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[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
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2021-09-28 11:34:20 -07:00 |
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tangxifan
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a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
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53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
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3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
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212c5bd642
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[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
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d0fe12fadd
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[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
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2021-09-22 10:03:39 -07:00 |
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tangxifan
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0450d57d82
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[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
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2021-09-20 16:05:01 -07:00 |
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tangxifan
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cd2978a434
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[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
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2021-09-20 11:13:02 -07:00 |
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tangxifan
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6be3c64f1c
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[Arch] Add an example architecture using the physical design friendly memory bank organization
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2021-09-09 09:22:27 -07:00 |
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tangxifan
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dcb89cb16b
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[Arch] Patch architecture due to missing mode bit definition
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2021-07-02 11:41:29 -06:00 |
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tangxifan
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fd85f956c9
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[Arch] Update k4n4 arch with true multi-mode flip-flop
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2021-07-02 11:08:39 -06:00 |
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tangxifan
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f77b81fe5b
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[Arch] recover the mem16k arch as it is used in other test cases
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2021-04-28 15:05:30 -06:00 |
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tangxifan
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117cea295d
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[Arch] Patch architecture to be compatible with pin names of DPRAM cell
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2021-04-28 11:28:23 -06:00 |
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tangxifan
|
ec4b60f3cc
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[Arch] Add example arch using 1-kbit DPRAM
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2021-04-28 10:47:17 -06:00 |
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tangxifan
|
be98775ae5
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[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
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2021-04-28 10:45:10 -06:00 |