tangxifan
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e48de682ed
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[core] fixed som ebugs
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2023-11-03 14:39:28 -07:00 |
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tangxifan
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3c6a4d34d8
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[core] code format
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2023-04-24 13:36:59 +08:00 |
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tangxifan
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715765d81b
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[core] code complete for top testbench generator on ccffv2 upgrades
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2023-04-24 13:34:44 +08:00 |
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tangxifan
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667d9df028
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[core] developing testbench generator for ccff v2
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2023-04-24 11:36:21 +08:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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bf1a81fbb5
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[FPGA-bitstream] add timer to computing intensive functions
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2022-05-25 14:52:32 +08:00 |
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tangxifan
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1c46a92559
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[FPGA-Bitstream] Bug fix
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2021-10-09 21:59:56 -07:00 |
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tangxifan
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7810f376c8
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[FPGA-Bitstream] Patch code comments
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2021-10-09 21:03:01 -07:00 |
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tangxifan
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34575f7222
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[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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9693a269ee
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[FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
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2021-10-07 11:31:16 -07:00 |
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tangxifan
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fdd75c4ec8
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[FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks
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2021-10-05 17:54:07 -07:00 |
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tangxifan
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06b018cfe7
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[FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature
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2021-10-03 16:05:33 -07:00 |
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tangxifan
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3eb601531a
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[FPGA-Verilog] Many bug fixes
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2021-10-02 23:39:53 -07:00 |
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tangxifan
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f686dd1f60
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[FPGA-Bitstream] Do not reverse for now. Previous solution looks correct
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2021-10-01 23:12:38 -07:00 |
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tangxifan
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198517a898
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[FPGA-Bitstream] Bug fix on bitstream sequence for QuickLogic memory bank using shift registers
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2021-10-01 19:59:50 -07:00 |
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tangxifan
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2de6be44d6
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[Engine] Fixed a critical bug which causes bitstream wrong for QuickLogic memory bank when fast configuration is enabled
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2021-10-01 18:27:42 -07:00 |
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tangxifan
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9e5debabe1
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[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
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2021-10-01 16:23:38 -07:00 |
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tangxifan
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4f7ab01bf5
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[FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately
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2021-10-01 15:47:13 -07:00 |
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tangxifan
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96828e456a
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[FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong
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2021-09-30 22:07:46 -07:00 |
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tangxifan
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33972fc0ec
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[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
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2021-09-30 21:05:41 -07:00 |
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tangxifan
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43c569b612
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[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
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2021-09-30 14:47:21 -07:00 |
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tangxifan
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33e9b27cb8
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[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
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2021-09-25 20:22:27 -07:00 |
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tangxifan
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3cf31f1565
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[Engine] Fixed bugs
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2021-09-25 18:22:55 -07:00 |
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tangxifan
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386812777c
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[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
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2021-09-25 12:49:32 -07:00 |
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tangxifan
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8b72447dad
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[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
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2021-09-24 18:07:07 -07:00 |
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tangxifan
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4b8f5f294a
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[Tool] Capsulate fabric bitstream organization for configuration chain
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2021-04-10 14:28:31 -06:00 |
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tangxifan
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afa0e751da
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[Tool] Use alias for complex bitstream data types
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2021-04-10 14:12:02 -06:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
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e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |