2019-04-10 02:24:37 -05:00
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#!/bin/bash
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source .travis/common.sh
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set -e
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start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
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2019-08-31 22:42:31 -05:00
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mkdir build
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cd build
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2019-04-10 02:24:37 -05:00
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if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
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2019-08-25 02:28:21 -05:00
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cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
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2019-08-21 12:08:13 -05:00
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else
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2019-06-03 16:34:26 -05:00
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cmake .. -DCMAKE_BUILD_TYPE=debug
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2019-04-10 02:24:37 -05:00
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fi
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2019-08-31 22:42:31 -05:00
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make -j16
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2019-05-15 17:55:18 -05:00
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end_section "OpenFPGA.build"
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2019-08-31 23:53:42 -05:00
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2019-05-16 15:30:16 -05:00
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2019-08-31 23:36:18 -05:00
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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2019-05-16 16:05:34 -05:00
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cd -
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2020-04-12 13:57:13 -05:00
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###############################################
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# OpenFPGA with VPR7
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# TO BE DEPRECATED
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##############################################
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2019-11-01 12:09:35 -05:00
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echo -e "Testing single-mode architectures";
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2019-11-02 00:26:08 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
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2019-11-01 12:09:35 -05:00
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#python3 openfpga_flow/scripts/run_fpga_task.py s298
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echo -e "Testing multi-mode architectures";
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2019-11-05 17:31:42 -06:00
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python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
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2019-11-05 17:24:39 -06:00
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2019-11-01 12:09:35 -05:00
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echo -e "Testing compact routing techniques";
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2019-11-02 00:26:08 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
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2019-11-01 12:09:35 -05:00
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echo -e "Testing tileable architectures";
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2019-11-02 00:26:08 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
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2019-11-01 12:09:35 -05:00
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echo -e "Testing Verilog generation with explicit port mapping ";
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2019-11-02 00:26:08 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
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2019-11-01 12:09:35 -05:00
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2019-12-30 15:06:20 -06:00
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echo -e "Testing Verilog generation with grid pin duplication ";
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python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
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2020-04-12 13:57:13 -05:00
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###############################################
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# OpenFPGA Shell with VPR8
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# (Will replace all the old tests)
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##############################################
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echo -e "Testing OpenFPGA Shell";
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echo -e "Testing Verilog generation with simple fracturable LUT6 ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
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2020-04-12 15:08:24 -05:00
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echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
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2020-04-12 15:27:05 -05:00
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echo -e "Testing Verilog generation with hard adder chain in CLBs ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs
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echo -e "Testing Verilog generation with 16k block RAMs ";
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2020-04-12 15:32:09 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --debug --show_thread_logs
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2020-04-12 15:27:05 -05:00
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2020-04-12 15:37:08 -05:00
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echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/wide_dpram16k --debug --show_thread_logs
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2019-08-31 23:36:18 -05:00
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end_section "OpenFPGA.TaskTun"
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