OpenFPGA/.travis/script.sh

38 lines
1.2 KiB
Bash
Raw Normal View History

2019-04-10 02:24:37 -05:00
#!/bin/bash
source .travis/common.sh
set -e
start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
2019-08-31 22:42:31 -05:00
mkdir build
cd build
2019-04-10 02:24:37 -05:00
if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
2019-08-25 02:28:21 -05:00
cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
else
cmake .. -DCMAKE_BUILD_TYPE=debug
2019-04-10 02:24:37 -05:00
fi
2019-08-31 22:42:31 -05:00
make -j16
2019-05-15 17:55:18 -05:00
end_section "OpenFPGA.build"
2019-05-16 15:30:16 -05:00
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
2019-05-16 16:05:34 -05:00
cd -
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py s298
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 --debug --show_thread_logs
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
end_section "OpenFPGA.TaskTun"