Debug for Travis

.travis/script.sh

@@ -1,5 +1,15 @@
 #!/bin/bash
 
+# Set variables
+set benchmark = test_modes
+set include_netlists = _include_netlists.v
+set compiled_file = compiled_$benchmark
+set tb_formal_postfix = _top_formal_verification_random_tb
+set verilog_output_dirname = ${benchmark}_Verilog
+set log_file = ${benchmark}_sim.log
+
+$SPACER
+
 source .travis/common.sh
 set -e
 
@@ -20,29 +30,27 @@ else
   cmake ..
   make -j2
 fi
+end_section "OpenFPGA.build"
 
+$SPACER
+
+start_section "Verilog_test" "${GREEN}Testing..${NC}"
 # Begining of Verilog verification
-# Set variables
-set benchmark = test_modes
-set include_netlists = _include_netlists.v
-set compiled_file = compiled_$benchmark
-set tb_formal_postfix = _top_formal_verification_random_tb
-set verilog_output_dirname = ${benchmark}_Verilog
-set log_file = ${benchmark}_sim.log
-
 # Move to vpr folder
 cd vpr7_x2p/vpr
-
+echo "DEBUG_0"
 # Remove former log file
 rm $log_file
 rm $compiled_file
-
+echo "DEBUG_1"
 # Start the script -> run the fpga generation -> run the simulation -> check the log file
 source .regression_verilog.sh
 iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
+echo "DEBUG_2"
 vvp $compiled_file -j 16 >> $log_file
-
+echo "DEBUG_3"
 set result = `grep "Succeed" $log_file`
+echo "DEBUG_4"
 if ("$result" != "")then
   echo "Verification succeed"
   cd -
@@ -60,7 +68,6 @@ else
   fi
 fi
 # End of Verilog verification
-
-end_section "OpenFPGA.build"
+end_section "Verilog_test"
 
 $SPACER