2019-07-08 17:18:08 -05:00
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#! /bin/bash
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# Exit if error occurs
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set -e
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# Make sure a clear start
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pwd_path="$PWD"
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task_name="tuto"
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config_file="$pwd_path/configs/tutorial/${task_name}.conf"
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bench_txt="$pwd_path/benchmarks/List/tuto_benchmark.txt"
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rpt_file="$pwd_path/csv_rpts/fpga_spice/${task_name}.csv"
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verilog_path="${pwd_path}/${task_name}_Verilog"
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2019-07-10 11:37:05 -05:00
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architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml"
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architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml"
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2019-07-08 17:18:08 -05:00
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ff_keyword="FFPATHKEYWORD"
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2019-07-10 16:42:31 -05:00
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ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v"
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2019-07-08 17:18:08 -05:00
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dir_keyword="GENERATED_DIR_KEYWORD"
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rm -rf ${pwd_path}/results_OpenPithon
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2019-07-16 08:20:21 -05:00
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cd ${pwd_path}/arch
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2019-07-16 14:13:58 -05:00
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mkdir -p generated # create folder to save rewritten architecture
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2019-07-08 17:18:08 -05:00
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cd ${pwd_path}/scripts
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# Replace keyword in config and architecture files
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2019-07-10 11:03:30 -05:00
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perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file
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perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file
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perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file
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2019-07-10 16:42:31 -05:00
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echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path"
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2019-07-10 11:03:30 -05:00
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perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file
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2019-07-08 17:18:08 -05:00
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# SRAM FPGA
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# TT case
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2019-07-16 08:04:45 -05:00
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perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping
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2019-07-08 17:18:08 -05:00
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echo "Netlists successfully generated and tested"
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