The xlnx_pcie_xvc_execute_stableclocks() function can and
should be static.
Change-Id: I45fb1363caee1f1762b0b1ac2c6bc1bb0153b15b
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: http://openocd.zylin.com/5889
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This is a) broken and b) doesn't include anything other than the
(broken) target alias. Don't see any reason for it to exist.
Change-Id: I833635eeac392bf7c0c39f51ff2f76525ba2d406
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/5884
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The config_trace function has an out-parameter for generating the
prescaler for the TPIU. The STLink implementation wasn't always writing
it, causing the tpiu command to load uninitialized stack memory (minus
one) into the TPIU's prescaler register when 'external' was requested.
This change ensures that the out-parameter (and the other one,
trace_freq, which hadn't caused any buggy behavior for me) are written
every time.
Signed-off-by: Cliff L. Biffle <cliff@oxide.computer>
Change-Id: I222975869b1aa49cc6b1963c79d5ea0f46522b8c
Reviewed-on: http://openocd.zylin.com/5656
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Now that it’s possible to start profiling from either a running or a
halted state, rather than unconditionally halting after profiling
finishes, it makes more sense to restore the processor to whatever state
(running or halted) it was in before profiling started.
Change-Id: If6f6e70a1a365c1ce3b348a306c435c220b8bf12
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5237
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The Cortex-M implementation of profiling contains a bunch of
conditionals and checks to handle both chips which have PCSR and chips
which do not. However, the net effect of the non-PCSR branches is
actually exactly the same as what target_profiling_default does. Rather
than duplicating this code, just detect the situation where PCSR isn’t
available and delegate to target_profiling_default.
Change-Id: I1be57ac77f983816ab6bf644a3cfca77b67d6f70
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
There are a handful of implementations of profiling. There is the
default implementation, which repeatedly halts and resumes the target,
sampling PC each time. There is the Cortex-M implementation, which
uses PCSR if available, otherwise falling back to halting and resuming
and sampling PC. There is the OR1K implementation, which reads NPC
repeatedly. Finally, there is the NDS32 implementation which uses some
kind of AICE commands with which I am unfamiliar.
None of these (with the possible exception of the NDS32
implementation) actually require the target to be halted when starting
profiling. The Cortex-M and OR1K actually resume the target as pretty
much their first action. The default implementation doesn’t do this,
but is written in such a way that the target just flips back and forth
between halted and running, and the code will do the right thing from
either initial state. The NDS32 implementation I don’t know about.
As such, for everything except NDS32, it is not really necessary that
the target be halted to start profiling. For the non-PCSR Cortex-M and
default implementations, there is no real harm in such a requirement,
because profiling is intrusive anyway, but there is no benefit. For
the PCSR-based Cortex-M and the OR1K, requiring that the target is
halted is annoying because it makes profiling more intrusive.
Remove the must-be-halted check from the target_profiling function.
Add it to the NDS32 implementation because I am not sure if that will
break when invoked with a running target. Do not add it to any of the
other implementations because they don’t need it.
Change-Id: I479dce999a80eccccfd3be4fa192c904f0a45709
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5235
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
HWID is a part of 32 bit CONFIGID register. hwid member of struct nrf5_info
was typed uint32_t to enable direct CONFIGID read and masked afterwards.
Change to uint16_t to unify with hwid in struct nrf5_device_spec
and RM description.
Change-Id: Ib720d3ce23c301aee41d074ea78a6f00a23aed68
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5589
Tested-by: jenkins
nRF52 devices indicate a flash error by emitting hard fault
exception (unlike nRF51 series).
Change error message when NVMC READY read fails. A hard fault
from flash erase/write operation is detected here.
Check exit point of the flash write algo to ensure a failed
write is recognised.
Change-Id: I637eda268a6bf45f7f41bcb9dcd82db8f5cb41b4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5587
Tested-by: jenkins
nRF51 devices have a clumsy flash protection based on UICR CLENR0.
A code running in RAM can write to a protected flash region without
any hint the protection gets violated.
NVMC flash page erase obeys protection setting but fails absolutely
silently.
Before this change the first problem was not addressed in the code.
To justify the second one, protection was loaded during probe,
after protection setting and after a mass erase.
Move protection updates to the beginning of erase/write operation
and limit them to nRF51 series only. Check for protected sectors
before write.
The change also fixes the problem of 'nrf5 mass_erase' on
nRF52833/840 devices. They use ACL flash protection, which is not
supported in nrf5 driver. mass_erase then looked like it failed.
Change-Id: Ie58cda68eb104d410b02777c3df5b343408e2666
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5522
Tested-by: jenkins
Protection setting has not ever worked. UICR CLENR0 register cannot
be simply written but has to programmed because it resides in UICR
page of the flash.
Enable flash programming before writing CLENR0 and set back to r/o
afterwards.
Inform the user that reset might be required.
Change-Id: Ib0f96c74ba3583ac33f4394ddb57d8c8895adf53
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5586
Tested-by: jenkins
Handle Ctrl+K shortcut which clears the line from the cursor position
to the end of line.
Change-Id: I2ecff5284473cef7c11cf9cb7e1c0c97d55f6c1c
Signed-off-by: Brian Brooks <brooks.brian@gmail.com>
Reviewed-on: http://openocd.zylin.com/5868
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
With help of actionpoint mechanism now it is possible to introduce
watchpoints support for ARC.
Change-Id: I5887335d0ba38c15c377bc1d24a1ef36e138cf65
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5867
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added comment to ti-icdi.cfg specifying how to get serial and an example of
specifying hla_serial for ti-icdi devices. This has been implemented in revision
2121a8f92969804611412b705af8114697a647dc
Change-Id: I648458a4dea176beae6a3f1a4e5641d0206077eb
Signed-off-by: John Pham <jhnphm@gmail.com>
Reviewed-on: http://openocd.zylin.com/2528
Tested-by: jenkins
Reviewed-by: Matthew Trescott <matthewtrescott@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Used jtag_libusb_open from libusb_helper.h instead of
libusb_open_device_with_vid_pid to get device handle,
as well as managing context, i.e. similar to stlink_usb.
Direct calls to libusb1 are left in for the moment.
(When this Gerrit revision was originally created,
the jtag_libusb_ wrappers did not return error conditions.)
Tested w/ a TM4C123GXL board
Change-Id: I71e9a366356c125444d4813e58ddd9b6c6498bf0
Signed-off-by: John Pham <jhnphm@gmail.com>
Signed-off-by: Matthew Trescott <matthewtrescott@gmail.com>
Reviewed-on: http://openocd.zylin.com/2527
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
nrf52_recover was merged in pre "Handle Tcl return values consistently"
state - remove ocd_ prefixes.
Erase and unlock sequence was changed to comply Nordic semiconductor
recommendation:
https://infocenter.nordicsemi.com/index.jsp?topic=%2Fnwp_027%2FWP%2Fnwp_027%2FnWP_027_erasing.html
Change-Id: Ic54236c27cf25ad8091e9e572ba1ef846f0d47c2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Pieter De Gendt <pieter.degendt@gmail.com>
Reviewed-on: http://openocd.zylin.com/5845
Tested-by: jenkins
Reviewed-by: Pieter De Gendt <pieter.degendt@gmail.com>
Bit 2 of control register is used if the processor includes the FP
extension
Change-Id: Ie21bc9de8cae5bad9d841e1908eff3aa0bb29d4b
Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai>
Reviewed-on: http://openocd.zylin.com/5853
Reviewed-by: Sylvain Chouleur <sylvain.chouleur@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This lets a user see exactly what period of time was sampled, without
having to guess how much time the target was ignored in between bursts.
Change-Id: I5c0639528636bf1a88f249be3ba59bec28c001e2
Signed-off-by: Tim Newsome <tim@sifive.com>
* Allow riscv_semihosting without 16 bit access to memory with instrustions
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* rename *_by_any_size to riscv_*_by_any_size
The script was telling me:
```
WARNING: use relative pathname instead of absolute in changelog text
\#20: FILE: contrib/cross-build.sh:25:
-# /path/to/openocd/contrib/cross-build.sh <host-triplet>
```
In the change where I changed that line to not refer to an absolute
path.
Change-Id: I1a21af5c36d9aeb01d3e819bfe2b06eb00466467
Signed-off-by: Tim Newsome <tim@sifive.com>
Used histogram diff strategy, which was much better than the default.
Conflicts:
doc/openocd.texi
src/flash/nor/fespi.c
src/jtag/drivers/libjaylink
src/rtos/rtos.c
src/target/riscv/batch.c
src/target/riscv/encoding.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/target.c
tcl/target/gd32vf103.cfg
Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
The commit b68674a1da ("Upstream tons of RISC-V changes.") was
proposed well before commit 3ac010bb9f ("Fix debug prints when
loading to flash"), but the merge got in different order.
After latest merge, the master branch fails to compile.
Fix the compile error.
Change-Id: Ia3bd21d970d589343a3b9b2d58c89e0c49f30015
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5856
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.
Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.
I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.
Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Add support for ATSAMG55x19 Rev.B.
Both chips have nearly the same cidr, however, Rev.B has an incremented version.
Change-Id: I5939c41fa5d54c4d3bfb850964974b878f709d13
Signed-off-by: Benedikt-Alexander Mokroß <mokross@gessler.de>
Reviewed-on: http://openocd.zylin.com/5825
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
* Do not throw error if RISC-V tselect unimplemented
A RISC-V hart without Trigger Module may not implement any of the
associated CSRs such as tselect according to the specification.
riscv_enumerate_triggers previously threw an error in this case, but
only on the first invocation due to r->triggers_enumerated being set
regardless of this. Due to the propagation of this error condition to
disable_triggers and riscv_openocd_step, such a hart would remain
halted after the first 'step' (or 'continue') of a debug session.
This problem can be reproduced with the Ibex RISC-V CPU when
the DbgTriggerEn parameter is set to zero.
This commit changes the behavior of riscv_enumerate_triggers to
return ERROR_OK when tselect was not readable. This fixes the
described malfunction.
Change-Id: Ie813cb119b03702fe708801b5f3581f9bf337243
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
* Add debug message if RISC-V tselect not readable
Change-Id: Ic3ad5bff9de5c50142cad983f351ce0099cec5c8
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
* RISC-V triggers: continue if tselect is unreadable
In riscv_enumerate_triggers, even if for one hart tselect cannot be
accessed, other harts might provide trigger support. For this reason,
"continue;" is the appropriate action on a read failure of tselect,
which indicates that triggers are not implemented, instead of
"return ERROR_OK;".
Change-Id: Ied56f3e237b76195a15bfde159532eda9d347d21
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
The function adiv5_jim_configure() casts the void pointer
'target->private_config' to a struct adiv5_private_config pointer.
This is tricky in case of aarch64, where the private data are in a
struct aarch64_private_config that has as first element the struct
adiv5_private_config.
While the current solution is working fine, it's not clean and
requires special attention for any further code development.
Override 'target->private_config' to the correct pointer while
calling adiv5_jim_configure().
Change-Id: Ic2fc047dd1e57013943d96e6d5879a919d1eb7b3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5847
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Change aarch64 to use ap-num setting if provided. Fall back to original
behavior of using first AP when ap-num is invalid.
Change-Id: I0d3624f75c86ba5fd5a322ac60856dbbb6e71eaf
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: http://openocd.zylin.com/5831
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Add memory sampling feature.
Currently only gets 10 samples per second, but the overall scaffolding
looks like it works.
Change-Id: I25a2bbcba322f2101c3de598c225f83c902680fa
* Basic memory sample speed-ups.
977 samples/second.
Change-Id: I6ea874f25051aca1cbe3aa2918567a4ee316c4be
* Add base64 dumping of sample buffer.
We can't just dump raw data, because the API we use to get data to the
"user" uses NULL-terminated strings.
Change-Id: I3f33faaa485a74735c13cdaad685e336c1e2095f
* WIP on optimizing PC sampling.
1k samples per second on my laptop, which is roughly double what it was.
Change-Id: I6a77df8aa53118e44928f96d22210df84be45eda
* WIP
Change-Id: I4300692355cb0cf997ec59ab5ca71543b295abb0
* Use small batch to sample memory.
5k samples/second. No error checking.
Change-Id: I8a7f08e49cb153699021e27f8006beb0e6db70ee
* Collect memory samples near continuously.
Rewrite OpenOCD's core loop to get rid of the fixed 100ms delay.
Now collecting 15k samples/second.
Change-Id: Iba5e73e96e8d226a0b5777ecac19453c152dc634
* Fix build.
Change-Id: If2fe7a0c77e0d6545c93fa0d4a013c50a9b9d896
* Fix the mess I left after resolving conflicts.
Change-Id: I96abd47a7834bf8f5e005ba63020f0a0cc429548
* Support 64-bit address in memory sampling.
* Support sampling 64-bit values.
* Better error reporting. WIP on 64-bit support.
* Speed up single 32-bit memory sample.
21k samples/second.
* WIP on review feedback.
Change-Id: I00e453fd685d173b0206d925090beb06c1f057ca
* Make memory sample buffers/config per-target.
Change-Id: I5c2f5997795c7a434e71b36ca4c712623daf993c
* Document, and add bucket clear option.
Change-Id: I922b883adfa787fb4f5a894db872d04fda126cbd
Signed-off-by: Tim Newsome <tim@sifive.com>
* Fix whitespace.
Change-Id: Iabfeb0068d7138d9b252ac127d1b1f949cf19632
Signed-off-by: Tim Newsome <tim@sifive.com>
* Document sample buffer full behavior.
Change-Id: Ib3c30d34b1f9f30cf403afda8fdccb850bc8b4df
Signed-off-by: Tim Newsome <tim@sifive.com>
* Actually clear the sample buffer in dump_sample_buf.
Change-Id: Ifda22643f1e58f69a6382abc90474659d7330ac5
Signed-off-by: Tim Newsome <tim@sifive.com>
* Use compatible string formatting.
Change-Id: Ia5e5333e036c1dbe457bc977fcee41983b9a9b77
Signed-off-by: Tim Newsome <tim@sifive.com>
The prescaler computation should round at the nearest integer
value, not to the next integer value.
Change-Id: I957e0774421211f3c4ba4b312738b1c67b87c4a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 051e80812b ("drivers/jlink: fix calculate_swo_prescaler formula")
Reviewed-on: http://openocd.zylin.com/5846
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
Search in XDG_CONFIG_HOME as per XDG Base Directory Specification
in addition to $HOME/.openocd.
On Darwin, search in ~/Library/Preferences/org.openocd/ which
appears to be one of the conventional locations.
Make $OPENOCD_SCRIPTS highest priority on all platforms, previously
it was only higher on WIN32.
Update the documentation to reflect the search order.
Change-Id: Ibaf4b59b51fdf452712d91b47ea2b5312bb5ada9
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3890
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Log lines already print a new line, so these superfluous \r\n result in
blank lines being printed in the log. Remove per review comment
request.
Change-Id: I8f5b20776634cf70ce4490fc4f732c916130928a
Signed-off-by: Karl Palsson <karlp@etactica.com>
Reviewed-on: http://openocd.zylin.com/5843
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Remember, don't cast your pointers between types of different sizes!
While the FreeRTOS handlers attempt to account for different pointer and
list widths, the types used are always fixed, so this will _remain_
broken if/when someone targets FreeRTOS on 8/16/64 bit targets. (Note
that this patch does not _change_ that, it was fixed to 32bit before as
well)
In the meantime, this properly handles 32bit reads on a mips BE system
(ath79) as well as remaining fully functional on x86_64.
Change-Id: I677bb7130e25dccb7c1bee8fabaee27371494d00
Signed-off-by: Karl Palsson <karlp@etactica.com>
Reviewed-on: http://openocd.zylin.com/5842
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This driver provides support for Cadence JTAG BFM
The "jtag_dpi" driver implements a JTAG driver acting as a client for the
SystemVerilog Direct Programming Interface (DPI) for JTAG devices.
DPI allows OpenOCD to connect to the JTAG interface of a hardware model
written in SystemVerilog, for example, on an emulation model of
target hardware.
Tested on Ampere emulation with Altra and Altra Max models
Change-Id: Iaef8ba5cc1398ee2c888f39a606e8cb592484625
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/5573
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If a target is not examined, command vector_catch crashes while accessing
the debug_ap NULL pointer.
maskisr and reset_config commands don't require this check.
Change-Id: I949b6f6e8b983327dd98fbe403735141f8f0b5d6
Signed-off-by: Daniel Trnka <daniel.trnka@gmail.com>
Reviewed-on: http://openocd.zylin.com/5813
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* riscv: work around buggy hart states during reset in some DMs
As described in the comment this change adds, the GD32VF103 DM reports
that the hart is in more than one state while it is resetting. Because
of this, the current code acknowledges resets before they actually
complete. This sometimes prevents havereset from getting cleared as
intended, leading to a spurious "Hart 0 unexpectedly reset!" message the
next time riscv_is_halted() gets called.
To work around this, check for the absence of the unavailable state
rather than the presence of the running or halted states. This behavior
is also arguably more true to the spec than what exists now: Section 3.2
states that "The system may take an arbitrarily long time to come out of
reset, as reported by allunavail, anyunavail."
Change-Id: I34e90a16233125608bce8e4c2414dbead637600e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* riscv: support custom reset-assert scripts
The reset-assert event is used, if present, to override the default
reset logic for ARM and MIPS cores. Do the same for RISC-V so that
devices with buggy ndmreset functionality (like GD32VF103) or
nonstandard reset sequences can specify the appropriate logic in Tcl.
Change-Id: I5e12077d67509853edb8ef3ad3f037f293a5fbb6
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* tcl/target: support GD32VF103 RISC-V MCU
The GD32VF103 is a low-cost 32-bit RISC-V microcontroller with
peripherals that are more-or-less compatible with the STM32F103 ARM
microcontroller. It is available on several low-cost dev boards, such as
the Sipeed Longan Nano, which is what I am testing on.
Add initial support for this chip, including a workaround for a buggy
ndmreset line (i.e. one that doesn't actually trigger a reset) in its
integrated debug module. Use the existing GD32VF103 flash driver that
was ported from the vendor's code in commit 48e40f3513 ("Add support
for GD32VF103 flash").
Change-Id: Iadac47ceb5437b8e18f3d35901388f10fef9f876
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* tcl/target/gd32vf103: add main flash alias
The GD32VF103 creates an alias to either main flash or the bootloader at
0x0, depending on how it was booted. As such, we want to indicate to
debuggers that the memory at 0x0 is flash and so cannot support software
breakpoints. To do this, add an alias to the main flash in the config.
This isn't strictly accurate in the case where we're running the
bootloader, but it still suits our purpose of fixing breakpoint
behavior.
Change-Id: I9eb8462d354f096eee231c0e5e2bffa538a5903e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* Improve riscv expose_[csrs|custom] commands
* Add option to specify custom name for registers.
* Allow to call commands multiple times without loss of previous data.
* Make sure the commands can only be used in the config phase (before "init").
* Validity checks and warnings.
* Change commands to be per target.
* Fix memory leaks.
* Also fix unrelated memory leaks to keep valgrind happy.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* fixes after review
* improve error message
This seems to be completely unused in these two files. It was probably
accidentally copied from riscv-011.c, where it is used.
Change-Id: I3f7ad8b2d26b005d3ea4438e2b3ec46a6c801792
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
These comments appear to have been copied from riscv-011.c, for which
they are accurate. However, it makes no sense to also have them in
riscv.c, because 1) none of the things described are actually in
riscv.c; and 2) riscv-013.c has an entirely different code structure,
meaning everything in the comment is an implementation detail of
riscv-011.c. Remove the copy in riscv.c and just leave the one in
riscv-011.c.
Change-Id: I2873af1522482681325525040b3caad2ddddce9d
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
a) TPIU_ACPR is defined as:
SWO_baudrate = TRACECLKIN/(TPIU_ACPR +1)
b) TPIU_ACPR is set by armv7m_trace_tpiu_config()
target_write_u32(target, TPIU_ACPR, Prescaler-1), so
TPIU_ACPR = Prescaler-1
Replacing TPIU_ACPR in a), we get:
SWO_baudrate = TRACECLKIN/Prescaler, so
c) Prescaler = TRACECLKIN/SWO_baudrate
The Prescaler calculated by calculate_swo_prescaler() is greater by 1:
Prescaler = TRACECLKIN/SWO_baudrate + 1
The second problem is that even in situations when
an exact baudrate match is possible,
the resulting TRACECLKIN/Prescaler already has a 3% deviation.
For example, TRACECLKIN=88000000, SWO_baudrate=500000,
calculate_swo_prescaler will return Prescaler=171.
The correct value should be Prescaler=176 (TPIU_ACPR=175).
Might be related to https://sourceforge.net/p/openocd/tickets/263/
Change-Id: Ib4d6df6e34685a9be4c2995cb500b2411c76e39b
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/5807
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
STM32H72x/73x flash is similar to STM32H74x/75x,
except STM32H72x/73x devices have only one single flash bank.
Change-Id: I3d3422dc60234f8273172924f426200210f388cc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5792
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Moritz Fischer
Karl Palsson
Cliff L. Biffle
Christopher Head
Tomas Vanek
Diego Herranz
Brian Brooks
Evgeniy Didin
John Pham
Tarek BOCHKATI
Sylvain Chouleur
Tim Newsome
Samuel Obuch
Antonio Borneo
Benedikt-Alexander Mokroß
Tobias Kaiser
Kevin Yang
Andreas Fritiofson
Karl Palsson
Kevin Burke
Daniel Trnka
Mete Balci
Ulrich-Lorenz Schlüter
Jan Kowalewski
Tom Hebb
Adrian Negreanu