Commit Graph

4169 Commits

Author SHA1 Message Date
Tim Newsome 84365e65e5 Remove riscv_info_t.current_hartid
This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).

This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.

Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-30 10:21:38 -07:00
Tim Newsome 550a66e720
Use LOG_TARGET_FOO() functions in more places. (#731)
Change-Id: Id2266dbfb6209bf0676f28e7383a12705ce2a70e
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-29 15:09:49 -07:00
Tim Newsome 23df83e830
Merge pull request #727 from riscv/poll_backoff
Make poll backoff time based.
2022-09-27 10:13:12 -07:00
Tim Newsome e53fd14f50
Merge pull request #733 from en-sc/en-sc/remove-erroneous-debuglog
Remove incorrect debug_log in wait_for_idle
2022-09-27 10:00:40 -07:00
Evgeniy Naydanov fb7c8b310a Remove incorrect debug_log in wait_for_idle
According to RISC-V External Debug Support Version 0.13.2 (paragraph
3.12.6), cmderr field contains a valid value only if busy is 0, so it is
incorrect to analize it on timeout.
2022-09-26 13:52:53 +03:00
Evgeniy Naydanov 137141249b Propagate error code in register_read/write_direct
In some cases error code returned by riscv_program_insert was ignored
2022-09-26 13:37:45 +03:00
Tim Newsome 3c5be531df Don't use const on temporary variable.
It's not part of OpenOCD style:
https://review.openocd.org/c/openocd/+/6319/5..10/src/target/aarch64.c#b1500

Change-Id: Ifb612a942507ca5ed8cac3e3ec59e0e14b0298ed
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-22 09:59:15 -07:00
Tim Newsome b7738370b7 Make large if() more readable.
Change-Id: Ie43400387ab9f290e744ebaa09786612237e6c7e
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:48:09 -07:00
Tim Newsome fa1abc63d2
Add explanatory comment.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:44:10 -07:00
Tim Newsome 89746e111b
Fix comment indent.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:43:51 -07:00
Tim Newsome 4004db5d3a Make polling_interval unsigned.
Hopefully fixes win32 build.

Change-Id: I13d6d475f03bada96b2eb943f2c16df05413d34f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-16 16:52:11 -07:00
Tim Newsome 639e68a621 Make poll backoff time based.
Requested in https://review.openocd.org/c/openocd/+/6964.
I'm making the change here so I have a chance to test it properly before
pushing it upstream.

A nice effect of this change is that we avoid some unnecessary polling
early on when gdb is connecting and we would poll once every time we
send gdb a qXfer packet.

Change-Id: I4bdb9f05839e8c1e01ff6dde49d6589595418095
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-16 15:19:21 -07:00
Tim Newsome 8832d4be97 Add error message when dmstatus read times out.
Otherwise OpenOCD simply doesn't work without giving any indication why.

Change-Id: I21703fc1a0d9bed2f59da95f8a8395fe139484a4
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-13 10:18:39 -07:00
Tim Newsome 911d68ef25
Don't read dmcontrol to set hartsel (#723)
* Don't read dmcontrol to set hartsel

We already know what dmcontrol should be. This addresses a long-standing
TODO. In a toy test, this reduced the number of scans by 10+%. (Most of
those are probably in poll(), so don't actually affect perceived
performance.)

Change-Id: I18e5ca391f0f5fb35f30d44dfef834e5a66aee20
Signed-off-by: Tim Newsome <tim@sifive.com>

* Make code easier to read

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-09-09 09:57:39 -07:00
Tim Newsome 7c0ca4dd53
Add copyright line to encoding.h. (#718)
Hopefully this will be the final version.

Change-Id: Ib2f8cd6f613c5e0f8e8bf7a16c3edbf2d9b439b2
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-25 11:04:46 -07:00
Tim Newsome 7a16947969
encoding.h license changed to BSD-3-Clause (#717)
See https://github.com/riscv/riscv-opcodes/pull/139

Change-Id: I77ae5ab369e6cde26ad44d177dcae38c0fbe08ef
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-22 08:56:44 -07:00
Tim Newsome fb523552d2
Update encoding.h again. (#713)
Now we get the license comment on the first line, which is required.

Change-Id: I54414db3c89ee6027e159ce9348459bc923b8595
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-18 10:10:49 -07:00
Evgeniy Naydanov 52177592f9
Fix overflow issue in write_memory_progbuf (#714)
If range's upper bound was equal to 2^64 or the range was wrapping around 0
(which is perfectly legal), writes were not performed due to riscv_addr_t
overflow.
2022-08-01 08:46:36 -07:00
Tim Newsome 793def24c5
Properly set dmcs2.grouptype. (#712)
In #697 this had gotten inverted.

Change-Id: Id86e2cfee0d15c1f05846c1fd5ac83dde26575a2
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-25 15:54:49 -07:00
Tim Newsome 969f112321
Update debug_defines.h. (#711)
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.

Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-18 09:20:22 -07:00
Tim Newsome aaf0620479
Update with latest encoding from riscv-opcodes (#710)
This gets us the new license header, which was requested upstream.

Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-08 13:02:13 -07:00
Jan Matyas 6d359afde4
Fix: Prevent segfault in riscv_invalidate_register_cache for non-examined targets. (#692)
The segfault could be triggered if:

- At least one target failed to get examined (therefore does not have the
  register cache set up yet),

- and "reset" TCL command was issued, which internally tries to
  invalidate the register cache.

Minor cleanup: "registers_initialized" member removed from riscv_info_t
because it is not used anywhere.

Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-06-16 09:58:45 -07:00
Tim Newsome d85a4e8098
Remove unused code. (#707)
Change-Id: I3961a62c0c51200ff3241265d9ea3e69492bdc4e
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-06-15 10:22:19 -07:00
Antonio Borneo 7cc79a8d62 arm_adi_v5: check for calloc() return value
In function adiv5_jim_configure() check that calloc() returns a
valid allocated memory pointer.

Change-Id: I97287e168834693900341add9d9eb9a5f38c55b4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7014
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:55 +00:00
Antonio Borneo 95135b39cc arm_adi_v5: fix scan-build warning [3/3]
While scan-build complains that dap_p or ap_num_p could be NULL,
the current code never passes NULL pointers.
Add an assert() to silent scan-build and prevent any further use
of the function with incorrect parameters.

Change-Id: I656810dddcea61e85d85b13efb114f7607ef837c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7012
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:29 +00:00
Antonio Borneo aee7c70a1a arm_adi_v5: fix scan-build warning [2/3]
Commit d01b3d69ec ("arm_adi_v5: separate ROM table parsing from
command output [3/3]") introduces a new scan-build warning because
removing one return in case of error causes using uninitialized
values.

Add back the return on error.

Change-Id: I10ddc548b756d34aaccc0511f091b4caa5ec271a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: d01b3d69ec ("arm_adi_v5: separate ROM table parsing from command output [3/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7011
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:17 +00:00
Antonio Borneo 63e22d5fb9 arm_adi_v5: fix scan-build warning [1/3]
Commit 21f7885d1c ("arm_adi_v5: separate ROM table parsing from
command output [1/3]") introduces a new scan-build warning because
continues the execution even when dap_get_debugbase() returns
error. The value of 'apid' can be uninitialized:

	5th function call argument is an uninitialized value

Check the return value and quit on error.
While there, remove the useless initialization of 'dbgbase' that
was apparently required for the same problem.

Change-Id: Iade26a152925ee0f1bf114ed829b94f7ed5b254f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 21f7885d1c ("arm_adi_v5: separate ROM table parsing from command output [1/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7010
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:01 +00:00
Tomas Vanek 7e9e5dca07 target/riscv: drop unused variable registers_initialized
Change-Id: If7bfe38ac273ce9e54003e003807e128cced1568
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6995
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-04 08:20:09 +00:00
Erhan Kurubas 78c87f5e81 target: add Espressif ESP32-S2 basic support
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-06-04 08:18:44 +00:00
Tarek BOCHKATI b470b664ca cortex_a: get rid of not needed log messages
when using semi-hosting with cortex_a this LOG_INFO pollutes openocd
console, so just reduce the log level of this message.

Change-Id: I91aa70492f4e361b25a0e5517d0cf73f2f8ed599
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://gerrit.st.com/c/stm32ide/official/openocd/+/248225
Tested-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6993
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-03 23:46:21 +00:00
Tomas Vanek cc8b491856 flash/nor/core, target: don't ask for working mem if no target algo
The command 'flash erase_check' showed the message
'Running slow fallback erase check - add working memory'
even in the case the target didn't implement blank_check_memory.

Change return code of target_blank_check_memory() in this case
and sense it in default_flash_blank_check() and show a message
without a request for working memory.

Change-Id: I7cf9bf77742964b4f377c9ce48ca689e57d0882f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6765
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-05-29 15:47:21 +00:00
Tim Newsome bce93f6d51 Give each SMP group a unique number.
This helps e.g. if there are 8 cores, and cores 0--3 are in one SMP
group while 4--7 are in another group. (And there are 2 gdb instances
connected, one debugging the first group, and one the second.)

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7b6c9382eadf964529105eaf0411a42d48768668
Reviewed-on: https://review.openocd.org/c/openocd/+/6979
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-27 22:52:35 +00:00
Tim Newsome 5c34da1415
Use new debug_defines.h (#703)
* Update debug_defines from the spec.

Now it includes constants for field values, so use them instead of
duplicating that here.

Change-Id: I2fca6e89f25123c39d4bf483b8244e47aefb0f88

* Remove unused #defines

Change-Id: Id20351851c9ed2c3aa82ccf8c04b604bef11692a

* Use debug spec constants in a few more places

Change-Id: Ic4578729c89e3c6a26a72772e1635c5345bd6a52
Signed-off-by: Tim Newsome <tim@sifive.com>

* Use macros for trigger action types.

Which were added with the very latest debug_defines.h.

Change-Id: I47f73e11d2ec529c720f2e1df05f7b0d3026e43a
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-05-25 10:08:43 -07:00
Erhan Kurubas ce5027ab01 semihosting: add semihosting_basedir command
This command allows users to set base working directory for the
semihosting I/O operations.Default is the current OpenOCD directory.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I80c5979e4c96d66cccdd12cc6fcd5f353e5c6b4d
Reviewed-on: https://review.openocd.org/c/openocd/+/6888
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-21 09:01:56 +00:00
Tomas Vanek 0f11f951e7 target: fix clang static analyzer warning
Removes Warning:	line 6482, column 12
1st function call argument is an uninitialized value

Use target ptr directly as checked in previous lines instead of
dereferencing head->target

Change-Id: I6804b776fd493af71f3098d702f9cdc7acb50151
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6970
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-21 09:00:05 +00:00
Tim Newsome 0fada02494
Correctly set target->smp. (#701)
This was broken by #684. Thanks to Jan for noticing.

Change-Id: I6ce115a6a333b93d7edb3ee44daae3f618d092e6
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-05-18 09:40:22 -07:00
Tomas Vanek 7d2ea186cf target/riscv: fix 'reset run' after 'reset halt'
'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
If hw reset line is configured e.g. 'reset_config srst_only'
the folowing 'reset run' halts:

 > gd32v.cpu curstate
 running

 > reset halt
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted <<<<---- wrong!!!

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 running

Clear DM_DMCONTROL_HALTREQ when acking reset.

Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6961
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-05-18 09:03:41 +00:00
Tim Newsome 6047fedc63
Change set_haltgroup() to more general set_group() (#697)
* Change set_haltgroup() to more general set_group()

Change-Id: Ib91a252ac63604e54b756f70c549ccd47241fd10
Signed-off-by: Tim Newsome <tim@sifive.com>

* Properly use enum.

Change-Id: I0edef6053fac388db38a22fe7557623fa93ec705
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>

* Style changes suggested in review.

Change-Id: I29e83d3dbef09cb971ec0355aff733191a6e4679
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-05-16 10:17:04 -07:00
wzgpeter a408bdc8db
fix: semihosting_fileio display the unsupported info (#699)
the abnormal info display below:
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0

the PC did not plus 4 before resume, which cause this
abnormal info popup.

Change-Id: I15c1e7426f1925e78f607c566976f9352216506f
Signed-off-by: Wu Zhigang <zhigang.wu@starfivetech.com>

Co-authored-by: Wu Zhigang <zhigang.wu@starfivetech.com>
2022-05-16 09:57:22 -07:00
Antonio Borneo 99293ebd15 aarch64: don't wait for smp targets halted in deassert reset
The function target_type::deassert_reset() is called for every
target after reset is deasserted. If the target fails to get
halted, we log a warning and issue a halt request for the target
itself.

Current code calls the generic target_halt() that:
- extends the halt to all the targets in the SMP node;
- waits for targets to halt.
This breaks the logic of running target_type::deassert_reset()
per target. Plus, waiting for targets to halt delays the call of
target_type::deassert_reset() for the next targets.

Replace the call to target_halt() with the aarch64 specific
function to halt the single target. Pass the parameter HALT_LAZY
to prevent the wait for target halted.
Similar solution is already implemented for cortex_a.

Change-Id: I446dc03cb91524c6d388db485bc2388177af77b6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6947
Tested-by: jenkins
2022-05-14 08:57:36 +00:00
Antonio Borneo a47d1f1b79 arm_adi_v5: add support for 64bit Class 0x9 ROM tables
Arm documentation does not explicitly report the order of the two
32bit words that compose the 64bit value. But both ADIv5 and ADIv6
specify that only little-endian is supported (ADIv5.2 obsoletes
the big-endian support). This change reads the 64bit value in
little-endian.

Detect the 64bit content and use it.

Change-Id: I723ec099c7e8c70c1f9a568e32ea867fcbf1f1db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6465
Tested-by: jenkins
2022-05-14 08:56:37 +00:00
Antonio Borneo d74f11dcd4 arm_adi_v5: replace dap_lookup_cs_component()
With the generic function for ROM table walk-through, reimplement
dap_lookup_cs_component().

Catch the code CORESIGHT_COMPONENT_FOUND and halt the search.
While there, drop two macros in arm_coresight.h, now unused.

Change-Id: I589ef7ae8a651d0c422ce7d0b4ed913713a8217e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6824
Tested-by: jenkins
2022-05-14 08:55:52 +00:00
Antonio Borneo 613f1c6abb arm_adi_v5: let dap_lookup_cs_component() to get AP dbgbase
Simplify the code in cortex_a and aarch64 by moving the call to
dap_get_debugbase() inside dap_lookup_cs_component().

This has the further effects:
- dap_get_debugbase() is not referenced outside arm_adi_v5.c and
  becomes static;
- dap_lookup_cs_component() looses one parameter;
- the coreid parameter 'idx' is passed as value;
- the caller in aarch64 don't have and don't print the irrelevant
  value of AP register APID;
- fixes the debug message in the caller in aarch64 to print the
  coreid value instead of always zero.

Change-Id: Ic7f0f643fdf067c059c8f2455a02ff18a3fed054
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6823
Tested-by: jenkins
2022-05-14 08:55:33 +00:00
Antonio Borneo 7351330a0f arm_adi_v5: abstract actions during ROM table parsing
Now all the actions (build command output) of command "dap info"
are decoupled from the ROM walk-through.
Pass the actions as a generic parameter to ROM walk-through code.
Put as private data every information that is only required by the
actions and not by the ROM walk-through.

Change-Id: I3b6ad112ea21296458c94aebbf91bf65bf6657a7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6822
Tested-by: jenkins
2022-05-14 08:54:53 +00:00
Antonio Borneo d01b3d69ec arm_adi_v5: separate ROM table parsing from command output [3/3]
This change only targets the output of rtp_rom_loop().

Change-Id: If9ac013798923428c3b897a969887e98b6935a2b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6821
Tested-by: jenkins
2022-05-14 08:54:36 +00:00
Antonio Borneo c83b94b2c8 arm_adi_v5: separate ROM table parsing from command output [2/3]
This change only targets the output of rtp_cs_component().
To easily propagate the coordinates of the CoreSight component,
add them in the struct that holds the register values.
While there, define a macro for the max depth of ROM tables.

Change-Id: I75e5ef4f9419da3192123aebcd61471c2af9374f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6820
Tested-by: jenkins
2022-05-14 08:54:25 +00:00
Antonio Borneo 21f7885d1c arm_adi_v5: separate ROM table parsing from command output [1/3]
In OpenOCD arm_adi_v5 we have already two implementations of code
for parsing the ADIv5 ROM table:
- in the commands "dap info" and "$dap_name info";
- in the function dap_lookup_cs_component().
Adding support for ADIv6 requires extending both implementations.

Moreover, current code does not handle few aspects of the ROM
parsing, e.g. the "Power Domain IDs".
To add such extensions both implementations should be touched.

I plan to add a command to parses (again) the ROM table and dump a
simple prototype of a configuration script for the target, useful
while analysing a new target.

Keeping aligned all these implementation would be too complex.

With focus to "dap info" command, decouple the part of code to
walk-through the ROM table from the code that creates the command
output.
The idea is to keep a single implementation for the walk-through
code, while parametrizing the output code to handle the generation
of a configuration script or the result of the function
dap_lookup_cs_component().

This change only targets the output of MEM-AP header
Further changes will target other parts of the code.

While there, add a message if MEM-AP is not accessible.

Change-Id: I112f637edfdb8688afb4e631297f6536da9604f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6819
Tested-by: jenkins
2022-05-14 08:54:02 +00:00
Antonio Borneo a73adb5241 arm_adi_v5: handle faulting entry in ROM table
ARM IHI0031F "Arm Debug Interface Architecture Specification"
chapter C2.6.1 "BASE, Debug Base Address register" reports:
	A debugger must handle the following situations as
	non-fatal errors:
	- ...
	- An entry in the ROM Table points to a faulting location.
	- ...
	Typically, a debugger issues a warning if it encounters
	one of these situations. However, Arm recommends that it
	continues operating. An example of an implementation that
	might cause errors of this type is a system with static
	base address or ROM Table entries that enable entire
	subsystems to be disabled, for example by a tie-off input,
	packaging choice, fuse, or similar.

Don't halt ROM table parsing if one entry causes an error; log the
error condition and continue to next entry.
Not sure if we have to send an ABORT before continuing.

Change-Id: I94fdb5b175bfb07dde378149421582b7e7cd5b09
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6818
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:53:35 +00:00
Antonio Borneo d4335071b8 arm_adi_v5: report sysmem on class 0x9 ROM tables
As Class 0x1 ROM table, also Class 0x9 ROM tables encodes a flag
for system memory access.

Detect the flag in rtp_cs_component() and dump the same message
for both type of ROM tables.
Extend rtp_read_cs_regs() to read ARM_CS_C9_DEVID.

Change-Id: Ic85d1ea068ed706ceedfd65076ff4c96d04e9792
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6817
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:52:30 +00:00
Antonio Borneo 209cb38aa1 arm_adi_v5: split ROM table loop from generic coresight
During ROM table parsing, each ROM table entry points to a
CoreSight component that can, in turn, be another ROM table.

Split the specific code for ROM table handling from the generic
CoreSight code.
Log an error if a ROM table entry cannot be read.

Change-Id: I5ad106a99b9c21ddb48b5b162ae87101e4f49878
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6816
Tested-by: jenkins
2022-05-14 08:51:07 +00:00
Antonio Borneo c3f6e21d5c arm_adi_v5: rework dap_read_part_id()
Rework dap_read_part_id() while preparing for reorganizing the
'ROM Table Parsing' (RTP):
- rename it with 'rtp' prefix;
- extends it to read other CoreSight registers, thus improving the
  overall speed by queuing more reads;
- reduce the list of arguments by using a struct;
- reorder the reads by increasing offset, potentially gaining
  speed using MEM_AP_REG_BDx and/or auto-increment;
- log a debug message in case of read error.

Change-Id: I6544ac7740b808a6c0fbacf97ac00b97f5bd3832
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6815
Tested-by: jenkins
2022-05-14 08:50:41 +00:00
Florian Fainelli 1fd2a6c7f5 arm_adi_v5: add support for display Class 0x9 ROM tables
ADI v5.1 and v6.0 permit the definition of CoreSight components (class 9
ROM entries).

dap_rom_display() is refactored a bit such that we always end up with
attempting to parse the ROM contents using the appropriate upper limit
for class 1 and 9 ROM types.

Change-Id: I4ba497b3807f1f11f06186eb6e61959ea3540c59
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6359
Tested-by: jenkins
2022-05-14 08:48:10 +00:00
Antonio Borneo fed329feec arm_adi_v5: describe Class 0x9 Device Architecture register
Use the list of values from ARM IHI0029E to decode and print the
Device Architecture register.
Add attribute 'unused' to the function, not used yet.

Change-Id: I7b1dd204bd1db671578c588372b667e23611876c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6463
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:43:51 +00:00
Antonio Borneo a785ca315b adi_v5_jtag: reduce verbosity on persistent WAIT
In case of AP not responding, e.g. not clocked, the first WAIT
reply is logged as:
	DAP transaction stalled (WAIT) - slowing down
then OpenOCD retries the transaction few times, until it timeouts.
At each retry it prints the message:
	DAP transaction stalled during replay (WAIT) - resending
Depending on JTAG speed and transport latency, the amount of log
messages can be quite annoying and not relevant.
The last printed line is at timeout:
	Timeout during WAIT recovery

Reduce the verbosity.

Change-Id: I5a7a337527c98b2450de59066b13713511c2894f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6814
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:43:30 +00:00
Antonio Borneo d796f5929c arm_coresight: define ARM_CS_CIDR_CLASS()
Right now it has a single use but it will soon be used more.

Change-Id: I9a819c65df467fc859e4b5251035a17ed33daa35
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6813
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:42:29 +00:00
Tomas Vanek 4c1919c566 target: document possibly unreachable target in deinit_target()
Change-Id: I95ff3d200bb2c8f5bc43a34c92726d9c47f8c172
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6953
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-07 11:04:45 +00:00
Antonio Borneo 7819834ace target: fix build with jimtcl 0.79
In jimtcl 0.80 the prototype of Jim_DictPairs() has changed.
The only code in OpenOCD that uses Jim_DictPairs() has been merged
recently and it only uses the current jimtcl syntax.

To allow compiling OpenOCD master branch with older versions of
jimtcl, detect the version of jimtcl and use the appropriate
syntax.

Change-Id: I6fc78303b6a4db064a97f326c46119f4568e88f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: dullfire@yahoo.com
Reviewed-on: https://review.openocd.org/c/openocd/+/6948
Tested-by: jenkins
2022-05-07 11:04:18 +00:00
Antonio Borneo b4f8d99c8d smp: deprecate legacy SMP core switching support
The deprecation was already in the documentation since v0.11.0
through commit 85ba2dc4c6 ("rtos/hwthread: add hardware-thread
pseudo rtos") but OpenOCD was not informing the user printing a
runtime message.

Remove the deprecated method from the documentation and print a
deprecated message at runtime.
There is no reliable way to print the same message in GDB console,
so we have to rely on user noticing it in the OpenOCD log.
Target is to remove the functionality after v0.12.0.

Change-Id: Idd2d9e3b6eccc92dcf0432c3c7de2f8a0fcabe9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6862
Tested-by: jenkins
2022-05-07 11:00:00 +00:00
Tim Newsome 9460f43dc3 Merge branch 'master' into from_upstream
Conflicts:
	tcl/target/gd32vf103.cfg

I kept our version, except I changed the flash device as happened in
mainline. Once this file settles down in mainline, we can copy it
wholesale into this fork.

Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
2022-05-03 13:41:55 -07:00
Tim Newsome b6dddfacc0
Merge pull request #694 from riscv/trigger_hit
Look at trigger hit bits to see which trigger was hit.
2022-05-02 09:40:07 -07:00
fatalc 12d1ad0c75 target/disassembler: update capstone include path to <capstone.h>
on macos (homebrew base) `pkg-config --cflags capstone` output with
`-I/opt/homebrew/Cellar/capstone/4.0.2/include/capstone`
gcc not find headers on parent "include" path,
causes build error `fatal error: 'capstone/capstone.h' file not found`
it's ok to change to <capstone.h> for all platforms.

Signed-off-by: fatalc <cnfatal@gmail.com>
Change-Id: Ia2e2058024d4fc1a57a8b4ea847c664d74f67efb
Reviewed-on: https://review.openocd.org/c/openocd/+/6946
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-30 17:53:30 +00:00
Marc Schink 8789513fa9 target/arm_cti: Fix error handling in 'cti create'
Handle JIM_CONTINUE return value of adiv5_jim_mem_ap_spot_configure(),
otherwise OpenOCD silently quits when an unknown option is provided.

Change-Id: I9b1351c0911e74999d8dd1260ede9760088510d7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6944
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-30 17:52:40 +00:00
Tim Newsome 1979ad5594 If we know which trigger hit, don't disassemble.
Change-Id: I1d7b6ffa91b0557e2e74e544e4b35033ed3e3553
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-04-30 09:59:46 -07:00
Tim Newsome 73199226df Report some triggers as hardware breakpoints.
Instead of reporting them all as watchpoints.

Change-Id: If43d282a168f64f8fed6f659bcebbe2ef72f23e9
2022-04-27 13:01:14 -07:00
Tim Newsome d67a5bf064 During polling, check which trigger has `hit` set.
Change-Id: If226810ed930e5d7a2bab277a9f5b0f3ded86ffa
2022-04-27 13:00:47 -07:00
Tim Newsome 68e41dc1c8 Remove empty line.
Change-Id: Id00bfd73363e60e109b339e86d620c1ed7d5198a
2022-04-27 12:59:43 -07:00
Tim Newsome edcfcab890 Add trigger_hit field to riscv_info
Change-Id: If4e1b5c37da4ab9301d91f41ba4789662b677a29
2022-04-27 12:58:57 -07:00
Tim Newsome a6f3212684 Create riscv_hit_trigger_hit_bit() function.
This goes through the triggers OpenOCD set to find out if one of them
has the hit bit set.

Change-Id: I5b9f1c19273c7d40392a0cc278277ca6c94d2eae
2022-04-27 12:58:09 -07:00
Tim Newsome dc320d26f0 Small code cleanup.
Change-Id: I563b7c62494987287b13d9ed52a923e6f49a64be
2022-04-27 12:46:09 -07:00
Tim Newsome e8b05455e2 Make watchpoint.unique_id a uint32_t
Now it matches breakpoint.unique_id.

Change-Id: I06f24b2cede2ee56bdeac8666b5235f923b18659
2022-04-27 12:41:13 -07:00
Tim Newsome bd266161ca Fix typo in comment.
Change-Id: If847aaedc704857f30220da8d6af703f1b57ad1d
2022-04-27 10:48:10 -07:00
Jan Matyas a213397323 target/image: fix - p_flags field in ELF64 segment headers is 64 bits wide
Fixed the reading of p_flags in ELF64 segment headers - that field
is 64 bits wide.

Change-Id: I053ca57d36efb54b7c638484acd6c7a2fbcbd05a
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6927
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-23 09:26:15 +00:00
Dolu1990 9d737af351
riscv: Add a option to specify the JTAG TAP tunnel IR (#690)
* riscv: Add a option to specify the JTAG TAP IR used to access the bscan tunnel.

Change-Id: Ice8798823313e2177e75473e62b06e7da74bbba2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

* risc-v: Add litex doc about the set_bscan_tunnel_ir command

Change-Id: I1237213f32886d20fc7d60d5ca1e2124953eaeda
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* risc-v: remove tunnel ir length assert when ir is set by the user

Change-Id: I2b33fc6205f37461ff1bd15601b460a2467ea32b
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* Open riscv: Add a option to specify the JTAG TAP tunnel IR

Typo

Co-authored-by: Tim Newsome <tim@sifive.com>

* riscv: Add a option to specify the JTAG TAP tunnel IR

typo

Co-authored-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Tim Newsome <tim@sifive.com>
2022-04-20 10:16:47 -07:00
Tim Newsome b7fdcd5e85 Fix build.
Change-Id: Ied627f264a46e64f82a81b54e70daac2ebc0b708
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-04-11 11:21:30 -07:00
Tim Newsome 00d7c7994a Merge branch 'master' into from_upstream
Conflicts:
	src/server/server.c
	src/target/breakpoints.c
	src/target/semihosting_common.c
	src/target/target.c

Change-Id: I48bd3608c688c69d8aac0667fc46e2de5466a9f1
2022-04-11 11:13:20 -07:00
Dolu1990 78b56e25c2
riscv: Increase batch allocation size to improve transfer speed. (#689)
Change-Id: I4cd1479f4d2f7b63cd594f5cef9d6b3d877d9015
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-04-11 07:58:35 -07:00
Antonio Borneo 3fa695be24 openocd: include config.h in every file .c
Including config.h as first is required for every C file.
Add it to the C files that still miss it.

Change-Id: I1a210e7d3a854958a85a290b086ad8a9f5176425
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6856
Tested-by: jenkins
2022-03-26 13:32:57 +00:00
Antonio Borneo 00d4699d0b arm_tpiu_swo: fix autodetection of SWO pin frequency
While the documentation reports that SWO pin frequency can be
omitted to let the adapter autodetect the value, the code wrongly
drops an error when pin frequency is not specified.

Don't require the pin frequency to be set at "enable", but verify
that the adapter has properly changes it to a valid value.

Change-Id: I3dfbe3256e8887ef4f03512769b06381cdc9db0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Karl Palsson <karlp@tweak.net.au>
Fixes: 184724d14e ("arm_tpiu_swo: add support for independent TPIU and SWO")
Reviewed-on: https://review.openocd.org/c/openocd/+/6310
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
2022-03-26 13:23:40 +00:00
Antonio Borneo 2cafa8be73 semihosting: fix mode flags for local host open()
Commit dbbac5f11d ("semihosting: use open mode flags from GDB,
not from sys/stat.h") fixes the conversion of the mode flags from
ARM semihosting encoding for SEMIHOSTING_SYS_OPEN to GDB mapping
for open().
Doing this, it breaks the conversion to local host's OS mapping
for open().

Split the conversion array to one for GDB and one for local host.
The local host conversion array is taken directly from the old
code.

Change-Id: I385321ddd32c3ac5cf6da3f1ce9eff76b05dd527
Fixes: dbbac5f11d ("semihosting: use open mode flags from GDB, not from sys/stat.h")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6870
Tested-by: jenkins
2022-03-26 13:21:19 +00:00
Jan Matyas 0a70e59cb8
Fix: Set proper debug_reason in deassert_reset() (#687)
* Fix checkpatch workflow: ignore changes in .github/

Ignore changes in .github/ directory when running checkpatch.

Checkpatch emits false alarms on substrings "CC:" found in *.yml
workflow files, apparently thinking it is a "Cc:" signature in
commit message.

Change-Id: Id977d5a8838797e4676758066af4825651c41a87

* Fix: Set proper debug_reason in deassert_reset()

The issue was visible for example when user's .cfg file ended
with "reset halt" command:

In such case, the hart would remain halted but the debug_reason would not be
updated and may retain an incorrect value, e.g. DBG_REASON_NOTHALTED.
In such cases, gdb_last_signal() would provide an incorrect reply to GDB.

Change-Id: Ie6f050295fb5cbe9db38b189c4bc385662acf5b4
Signed-off-by: Jan Matyas <matyas@codasip.com>

* Fix checkpatch workflow: add 'apt-get update'

Change-Id: Ic5843ec86d16a187d01970a3253caade3d13b7ab
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-03-23 09:47:57 -07:00
Antonio Borneo 92c4e634d7 breakpoints: fix build on -fno-inline
Some configuration of GCC could default to -fno-inline, causing
the build to fail after commit fb43f1ff4e ("target: Rework 'set'
variable of break-/watchpoints").

Switch the new inline functions to 'static inline', as it's widely
used in the rest of the code.

Change-Id: I8bf31045a137bd34ed825f4b2a9338eb3c70046d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fb43f1ff4e ("target: Rework 'set' variable of break-/watchpoints")
Reviewed-on: https://review.openocd.org/c/openocd/+/6881
Tested-by: jenkins
2022-03-19 11:35:32 +00:00
Marc Schink fb43f1ff4e target: Rework 'set' variable of break-/watchpoints
The 'set' variable name suggests a boolean data type which determines
whether a breakpoint (or watchpoint) is active. However, it is also
used to store the number of the breakpoint.

This encoding leads to inconsistent value assignments: boolean and
integer values are mixed. Also, associated hardware comparator
numbers, which are usually numbered from 0, cannot be used directly.
An additional offset is required to store the comparator numbers.

In order to make the code more readable and the value assignment more
consistent, change the variable name to 'is_set', its data type to 'bool'
and introduce a dedicated variable for the break-/watchpoint
number.

In order to make the review easier, the data types of various related
variables (e.g. number of breakpoints) are not changed.

While at it, fix a few coding style issues.

Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6319
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-19 09:14:39 +00:00
Tarek BOCHKATI b9526f1401 semihosting: permit redirection of semihosting I/O to TCP
This command permits the usage of a TCP port to perform debug and stdio
operations:
 - debug : READC, WRITEC and WRITE0
 - stdio : READ, WRITE

This will permit the separation of semihosting message from OpenOCD log,
and separate semihosting messages per core.

syntax: arm semihosting_redirect (disable | tcp <port> [debug|stdio|all])

this allows to select which operations to be performed via TCP (debug,
stdio or all (default)).

Note: for stdio operations, only I/O from/to ':tt' file descriptors are
redirected.

tested using netcat on ubuntu

Change-Id: I37053463667ba109d52429d4f98bc98d0ede298d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5562
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-19 09:11:05 +00:00
Antonio Borneo 99c77806fe server: change prototype of add_service()
To easily add new methods to a service, pass all the methods
through a struct.
While there, drop the typedef for the methods and add currently
unused new methods to support keep-alive and connections during
keep-alive.

No change in functionality.

Change-Id: I2b5e7140db95021f6e7201e9d631ee340c60b453
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6838
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2022-03-19 09:05:27 +00:00
Marc Schink e370e06b72 target: Deprecate 'array2mem' and 'mem2array''
Replace 'mem2array' and 'array2mem' with a Tcl wrapper that
internally uses 'read_memory' and 'write_memory'.

The target-specific 'mem2array' and 'array2mem' functions
remain for now.

Change-Id: If24c22a76ac72d4c26916a95f7f17902b41b6d9e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6308
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12 09:48:00 +00:00
Marc Schink 38183dc856 target/tcl: Add 'read_memory' and 'write_memory'
These functions are meant as replacement for 'mem2array' and
'array2mem'.

The main benefits of these new functions are:

 * They do not use Tcl arrays but lists which makes it easier
   to parse (generate) the data. See the Python Tcl RPC code
   in contrib as a negative example.

 * They do not operate on Tcl variables but instead return (accept)
   the Tcl list directly. This makes the C and Tcl code base
   smaller and cleaner.

 * The code is slightly more performant when reading / writing
   large amount of data. Tested with a simple Python Tcl RPC
   benchmark.

Change-Id: Ibd6ece3360c0d002abaadc37f078b10a8bb606f8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6307
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12 09:47:42 +00:00
Tarek BOCHKATI 4906176c77 cortex_m: use LOG_TARGET_XXX
Change-Id: I8be0f67442644031e6e8df3090d81af195caf82b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6672
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12 09:33:35 +00:00
Marc Schink 2586fec922 target/arm_tpiu: Fix usage of 'tpiu create'
Change-Id: I1ffad65a9e6d76f4d7fbbe249d8af3beb7e7692b
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6860
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:24:18 +00:00
Marc Schink 4a4ca07da7 target/arm_tpiu: Fix 'tpiu create' parameter check
The current implementation crashes when executing 'tpiu create'
without an object name due to an invalid memory access. Pass 'argv'
instead 'goi.argv' to fix the problem.

While at it, match the style of the error message to the style used for
other Tcl commands. Especially, make the 'name' parameter mandatory.

Change-Id: Ib2b233f8556934af61608ae93d6405585c2c40b7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6329
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-03-05 13:23:33 +00:00
Marc Schink 29e2a74516 target/arm_tpiu: Make error message easier to understand
Change-Id: Idddc31e34a67641c32d041c89d01fe2126ec5ddb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6328
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:23:00 +00:00
Marc Schink e8e62c5aca target/tcl: Add get_reg function
Change-Id: Id1be9554d1df2c07cec3161a0fd3a586fdf18246
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/5312
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:21:24 +00:00
Marc Schink da73280101 target/tcl: Add set_reg function
Change-Id: I97a01b93046cb7af289792489f77f5580312585a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/5313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:11:25 +00:00
Tim Newsome 9e097d0fc4
From upstream (#684)
* flash/nor/atsame5: add LAN9255 devices

Support Microchip LAN9255 devices with embedded SAME53J MCU.

Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Change-Id: Ia811c593bf7cf73e588d32873c68eb67c6fafad7
Reviewed-on: https://review.openocd.org/c/openocd/+/6811
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl/board: Add EVB-LAN9255 config

Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10
connector.

Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7
Reviewed-on: https://review.openocd.org/c/openocd/+/6812
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* aarch64: support for aarch32 ARM_MODE_UND

Fix:
unrecognized psr mode: 0x1b
cannot read system control register in this mode: (UNRECOGNIZED : 0x1b)

Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5
Reviewed-on: https://review.openocd.org/c/openocd/+/6808
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Combine register lists of smp targets.

This is helpful when you want to pretend to gdb that your heterogeneous
multicore system is homogeneous, because gdb cannot handle heterogeneous
systems. This won't always works, but works fine if e.g. one of the
cores has an FPU while the other does not. (Specifically, HiFive
Unleashed has 1 core with no FPU, plus 4 cores with an FPU.)

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I05ff4c28646778fbc00327bc510be064bfe6c9f0
Reviewed-on: https://review.openocd.org/c/openocd/+/6362
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* semihosting: use open mode flags from GDB, not from sys/stat.h

Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.

This patch has been tested with STM32F446.

Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* semihosting: User defined operation, Tcl command exec on host

Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.

Example usage:
- The user configures a Tcl command as a callback for one of the newly
	defined events (semihosting-user-cmd-0x10X) in the configuration
	file.
- The target can make a semihosting call with <opnum>, passing optional
	parameters for the call.

If there is no callback registered to the user defined operation number,
nothing happens.

Example usage: Configure RTT automatically with the exact, linked
control block location from target.

Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/smp: use a struct list_head to hold the smp targets

Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.

Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783
Tested-by: jenkins

* helper/list: add list_for_each_entry_direction()

Use a bool flag to specify if the list should be forward or
backward iterated.

Change-Id: Ied19d049f46cdcb7f50137d459cc7c02014526bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6784
Tested-by: jenkins

* target/riscv: revive 'riscv resume_order'

This functionality was lost in [1], which was merged as commit
615709d140 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.

Add convenience macro foreach_smp_target_direction().

Link: [1] https://github.com/riscv/riscv-openocd/pull/567
Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6785
Tested-by: jenkins

* doxygen: fix some function prototype description

Change-Id: I49311a643ea73143839d2f6bde976cfd76f8c67f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6830
Tested-by: jenkins

* Cadence virtual debug interface (vdebug) integration

Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: Include thread name as XML attribute

Explicitly providing a thread name in the "thread" element produces
better thread visualizations in downstream tools like IDEs.

Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I102c14ddb8b87757fa474de8e3a3f6a1cfe10d98
Reviewed-on: https://review.openocd.org/c/openocd/+/6828
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix small memory leak.

See https://github.com/riscv/riscv-openocd/pull/672

Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6831
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* server: remove remaining crust from dropped eCos code

Commit 39650e2273 ("ecosboard: delete bit-rotted eCos code") has
removed eCos code but has left some empty function that was used
during non-eCos build to replace eCos mutex.

Drop the functions and the file that contain them.

Change-Id: I31bc0237ea699c11bd70921660f960ee406ffa80
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6835
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* rtos: threadx: Add hla_target support for ThreadX

Tested with an AZ3166 dev board (which uses the STM32F412ZGT6) running
the Azure RTOS ThreadX demonstration system.

Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I44c8f7701d9f1aaa872274166321cd7d34fb1855
Reviewed-on: https://review.openocd.org/c/openocd/+/6829
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* .gitmodules: switch away from repo.or.cz

The host repo.or.cz is often offline, creating issues for cloning
and building OpenOCD from scratch.
Already 'jimtcl' developer has dropped repo.or.cz, triggering the
OpenOCD commit 861e75f54e ("jimtcl: switch to github").

Change also the link of the remaining submodules 'git2cl' and
'libjaylink' to their respective main repository.

Change-Id: Ib513237427635359ce36a480a8f2060e2fb12ba4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6834
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>

* flash/nor/stm32f2x: Fix erase of bank 2 sectors

This commit corrects the erase function for stm32f2x when dealing with
sectors in bank 2, for STM32F42x/43x devices with 1MB flash.

On STM32F42x/43x with 1MB flash in dual bank configuration, the sector
numbering is not consecutive. The last sector in bank 1 is number 7, and
the first sector in bank 2 is number 12.
The sector indices used by openocd, however, _are_ consecutive (0 to 15
in this case). The arguments "first" and "last" to stm32x_erase() are of
this type, and so the logic surrounding sector numbers needed to be
corrected.
Since the two banks in dual bank mode have the same number of sectors, a
sector index in bank 2 is larger than or equal to half the total number
of sectors.

Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18
Signed-off-by: Simon Johansson <ampleyfly@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6810
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* target/cortex_m: fix target_to_cm() helper

The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.

It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.

Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/armv7m,cortex_m: introduce checked arch_info cast routines

target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.

Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.

Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/cortex_m: add Cortex-M part number getter

The getter checks the magic numbers in arch_info to detect eventual
type mismatch.

Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* flash/nor/stm32xx: fix segfault accessing Cortex-M part number

Some of STM32 flash drivers read Cortex-M part number from
cortex_m->core_info.
In corner cases the core_info pointer was observed uninitialised
even if target_was_examined() returned true. See also [1]

Use the new and safe helper to get Cortex-M part number.

While on it switch also target_to_cm()/target_to_armv7m() to the safe
versions. This prevents a crash when the flash bank is misconfigured
with non-Cortex-M target.

Add missing checks for target_was_examined() to flash probes.

[1] 6545: fix crash in case cortex_m->core_info is not set
    https://review.openocd.org/c/openocd/+/6545

Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Fixes: f5898bd93f (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common)
Reviewed-on: https://review.openocd.org/c/openocd/+/6752
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* cpld: altera-epm240: Add additional IDCODEs

This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cpld: altera-epm240: Increase adapter speed

According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: Add support for ls1088a

The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: ls1088a: Add service processor

Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.

The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.

I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* board: Add NXP LS1088ARDB

This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: fix double free

Commit 6541233aa7 ("Combine register lists of smp targets.")
unconditionally assigns the output pointers of the function
smp_reg_list_noread(), even if the function fails and returns
error.
This causes a double free from the caller, that has assigned NULL
to the pointers to simplify the error handling.

Use local variables in smp_reg_list_noread() and assign the output
pointers only on success.

Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae
Fixes: 6541233aa7 ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6852
Tested-by: jenkins
Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* gdb_server: check target examined while combining reg list

Commit 6541233aa7 ("Combine register lists of smp targets.")
assumes that all the targets in the SMP cluster are already
examined and unconditionally call target_get_gdb_reg_list_noread()
that will in turn return error if the target is not examined yet.

Skip targets not examined yet.
Add an additional check in case the register list cannot be built,
e.g. because no target in the SMP cluster is examined. This should
never happen, but it's better to play safe.

Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a
Fixes: 6541233aa7 ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6853
Tested-by: jenkins
Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* flash/stm32l4x: fix maybe-uninitialized compiler error

using gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0 we get:
error: ‘retval’ may be used uninitialized in this function

fixes: 13cd75b6ec (flash/nor/stm32xx: fix segfault accessing Cortex-M part number)
Change-Id: I897c40c5d2233f50a5385d251ebfa536023e5cf7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix build.

Change-Id: Ia60246246dd859d75659a43d1c59588dbb274d46
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Co-authored-by: Julien Massot <julien.massot@iot.bzh>
Co-authored-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Co-authored-by: Zoltán Dudás <zedudi@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Jacek Wuwer <jacekmw8@gmail.com>
Co-authored-by: Ben McMorran <bemcmorr@microsoft.com>
Co-authored-by: Simon Johansson <ampleyfly@gmail.com>
Co-authored-by: Tomas Vanek <vanekt@fbl.cz>
Co-authored-by: Sean Anderson <sean.anderson@seco.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-03-03 10:03:55 -08:00
Erhan Kurubas 87c0cda00f
riscv: implement maskisr steponly command (#681)
* riscv: implement maskisr steponly command

Change-Id: I1a3b666d466b064460c3acc307a36485ce165601
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>

* riscv: restore triggers and irq mask inside step function

Change-Id: I4e1b0665f4f2f75e42a6191c61634bdfa19ae2fb
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>

* doc: update for riscv set_maskisr command

Change-Id: Ia7d3a6df846cfc4568d79558f719e93f038aee9b
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-03-01 10:05:54 -08:00
Tomas Vanek b53f5c2571 target/cortex_m: add Cortex-M part number getter
The getter checks the magic numbers in arch_info to detect eventual
type mismatch.

Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-02-25 20:26:56 +00:00
Tomas Vanek e4ba76a003 target/armv7m,cortex_m: introduce checked arch_info cast routines
target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.

Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.

Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-25 19:56:41 +00:00
Tomas Vanek 10b5ac9ccb target/cortex_m: fix target_to_cm() helper
The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.

It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.

Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-25 19:53:18 +00:00
Erhan Kurubas 64f3f8877e
riscv: call debug_execution related events (#679)
Change-Id: Ice7cdc816f3e568a6ba2db8f9101903b8f7a08ce
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-02-21 09:02:07 -08:00
Tim Newsome 435a652236
Merge pull request #678 from riscv/invalidate-progbuf-cache
fix progbuf cache: invalidate it when needed
2022-02-15 10:27:16 -08:00
Tim Newsome 2c0a65baa2 Fix small memory leak.
See https://github.com/riscv/riscv-openocd/pull/672

Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6831
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-14 15:13:11 +00:00