Commit fc2abe63fd ("armv7m: use generic arm::core_mode") adds
two special modes for ARMv6M and ARMv7M in struct arm_mode_data[].
While these modes do not have any additional register to be dumped
by command 'arm reg', the command still prints an header for these
modes but not followed by any register.
Detect the special modes for ARMv6M and ARMv7M and skip them to
avoid printing the useless header.
Change-Id: I04145769e5742624f143c910eebf9a6f6d8e3cdc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fc2abe63fd ("armv7m: use generic arm::core_mode")
Reviewed-on: http://openocd.zylin.com/5942
Tested-by: jenkins
Commit fed7131049 ("armv4_5: support weirdo ARMv6 secure monitor
mode") introduces the secure mode 28 of ARMv6 as a synonymous of
mode 22 (MON), but does not add it in the switch/case in command
'arm reg'.
When command 'arm reg' scans the array arm_mode_data[] on targets
without secure modes, it does not detect the new secure mode as
not supported by the architecture, thus triggers a segmentation
fault when it try to read the register's value from unallocated
memory.
Issue detected with target arm926ejs.
Add the new mode in the switch/case and treat it as the mode MON.
Change-Id: I2b72cc558e097879a7ee6ea601200bfda6b60270
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fed7131049 ("armv4_5: support weirdo ARMv6 secure monitor mode")
Reviewed-on: http://openocd.zylin.com/5941
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
From JEP106AZ, released on May 24, 2019.
Change-Id: I768b7077ec6abcd19ae1530b5715c7ea993add67
Signed-off-by: Boran Car <boran.car@hex-five.com>
Reviewed-on: http://openocd.zylin.com/5244
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Real Time Transfer (RTT) is an interface specified by SEGGER based on
basic memory reads and writes to transfer data bidirectionally between
target and host.
Every target that supports so called "background memory access", which
means that the target memory can be accessed by the debugger while the
target is running, can be used.
RTT is especially of interest for targets which do not support Serial
Wire Output (SWO) (e.g. ARM Cortex-M0) or where using semihosting is
not possible (e.g. real-time applications) [1].
The data transfer is organized in channels where each channel consists
of an up- and/or down-channel. See [2] for more details.
Channels are exposed via TCP connections. One or more RTT server can be
assigned to each channel to make them accessible to an unlimited number
of TCP connections.
The current implementation does not respect buffer flags which are used
to determine what happens when writing to a full buffer.
Note that the implementation is designed in a way that the RTT
operations can be directly performed by an adapter (e.g. J-Link).
[1] https://devzone.nordicsemi.com/tutorials/6/
[2] https://www.segger.com/jlink-rtt.html
Change-Id: I8bc8a1b381fb74e08b8752d5cf53804cc573c1e0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/4055
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reading of DPIDR is the very first operation after JTAG to SWD sequence.
Without this change if DPIDR read fails then swd connect fails.
Keep trying JTAG to SWD sequence and DPIDR read until success
or timeout 0.5 sec. It makes setting of adapter srst delay on SWD transport
mostly unnecessary.
Also test for ERROR_WAIT (which should not occur according to
IHI 0031E B4.3.2 but a quirk is known) and if bus is kept stalled
then issue abort to make the next connect possible.
Change-Id: Id8fe6618605bbeb4fed5061e987ed55de90a35f2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5730
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
If dap_dp_read_atomic() in 30 trials loop fails, dap->do_reconnect is set.
Following dap_dp_read_atomic() calls dap_queue_dp_read() which in case
of SWD transport calls swd_queue_dp_read(). It starts
with swd_check_reconnect() and it calls swd_connect() because
dap->do_reconnect is set. swd_connect() does some initialization,
reads DPIDR and calls dap_dp_init() again!
Moreover if dap_dp_init() is called from cortex_m_reset_(de)assert()
one level of recursion is necessary to reconnect the target.
Introduce dap_dp_init_or_reconnect() for use in cortex_m reset
and similar.
Remove loop of 30 atomic reads of DP_STAT to prevent unwanted recursion.
Change-Id: I54052fdefe50bf5f7c7b59fe751fe2063d5710c9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5729
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Every debug log of OpenOCD contains approximately 130 lines like:
Debug: 264 147 command.c:354 register_command_handler(): registering 'flash'...
Because only root name of the command is logged, most of lines is not
too informative. E.g. registering 'flash' is repeated 14 times.
Karl Passon submitted the patch [1] changing the logged cmd name from
root to lowest level. It makes the log better. Unfortunately we also have
'reset_config' and 'cortex_m reset_config' and similar which looks
equal in the log after [1].
Moreover [1] has not been reviewed for 5 years.
So my guess is that nobody uses that crap in debug log.
Save more than 10 kbytes in any debug log and make log analyse easier
by blocking log command in #if 0 block.
If some developer eventually needs to debug cmd registering he can easily
enable logging again.
[1] http://openocd.zylin.com/2765
Change-Id: Ib7e528aadd692fd0da2e3c005b4c5a484551b728
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5928
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
STM32L5 have 512 Kbytes of Flash memory with dual bank architecture.
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
NON-SECURE flash is located at 0x8000000 like L4 devices, so no
big change is needed (secure flash will be subject of another change).
Note: flash driver name is set stm32l5x, in order to extend the commands
with specific L5 commands (to manage TZEN for example ...)
Note: this works only when TZEN=0
Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639
Signed-off-by: Michael Jung <mijung@gmx.net>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5510
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This change is a preparation for STM32L5 support on top of L4 driver
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
flash_regs table is introduced within stm32l4_flash_bank struct in order
to get correct register offsets, by using the driver internal function
'stm32l4_get_flash_reg_by_index'.
To use efficiently register indexes, stm32l4 _[get|read|write]_flash_reg
functions are surcharged to accept register indexes.
IMPORTANT: stm32l4_write_option is not surcharged, and they always accept
the option register offset.
tested on NUCLEO-G474RE and STM32L4R9I-DISCO
Change-Id: I739d3e97d63b831af6aa569c5629db0000209551
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5509
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Avoid multiple definition of cmsis_dap_usb_backend and
cmsis_dap_hid_backend using 'extern'.
Move the prototypes in cmsis_dap.h.
Remove the useless #if/#endif around the prototypes.
Change-Id: I8d73fe148e2155620244bc887d4235e9af530e30
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5790
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
http://openocd.zylin.com/4831 has following problems in selecting
USB device/interface to connect:
- attempts connection to any device with user class and 2 bulk endpoints
- regardless of cmsis_dap_vid_pid or cmsis_dap_serial setting
connects to the first suitable device
Distinguish between real match and no filtering cases and use that info
appropriately.
Add debug messages to show why the interface is refused.
Move CMSIS-DAP interface string detection before checking of class/endpoints
to give more understandable debug log in the case the device is refused.
Keep track of reliable matches in both device and interface enumeration.
First search for the interface with CMSIS-DAP in the interface string.
If it fails, chose the first suitable interface.
Change-Id: Ia1aacd5631a9f5c5db580bfb5745ceb6240d61ad
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5789
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This change implements CMSIS-DAP v2 which works with raw USB bulk transfers.
The old driver is now split into a generic CMSIS part and a HID backend,
with a new raw USB backend for CMSIS-DAP v2.
New commands:
- cmsis_dap_backend (usb_bulk | hid | auto)
- cmsis_dap_usb interface <interface number>
Change-Id: I4218477b12ccbfe19c9b332321cd21394bf44e30
Signed-off-by: Mickaël Thomas <mickael9@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4831
Tested-by: jenkins
Change-Id: I4fea29f07f4d3b8b2578b538ef0eef5f1eea285f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5876
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
PSoC6 erases flash to 0x00 not more common 0xff, so a device
with erased flash loads xPSR.T=0 from the zeroed reset vector.
Wrong thumb bit value caused a target algorithm failed with HardFault.
The low level write to xPSR solved the problem only if xPSR cached
copy was not marked dirty.
Later commit 49bd64347a fixed T setting
for all Cortex-M target algorithms.
Since 49bd64 this part of code is useless as xPSR target_start_algorithm()
sets always xPSR dirty so the effect of the low level write is eliminated
(and proper setting of thumb bit is ensured in target_start_algorithm())
Change-Id: I68aea5e921fbc6203f2fe91a45f10d22869327de
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5875
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If a Cortex-M (not M0, M0+) target was stopped in the middle of
a conditional IT block or in the load/store multiple instruction,
cortex_m_debug_entry() used wrong xPSR bits to detect it and then
cleared 8 bits of the exception number from xPSR
- probably wrong bit mask again.
I believe clearing of the ICI/IT bits in cortex_m_debug_entry() has no
reason as Cortex-M does not use instruction injecting.
Remove the wrong code.
The change was originally a part of http://openocd.zylin.com/4862
It is now re-submitted as #4862 is not ready.
Change-Id: If91cd91d1b81b2684f7d5f10cf20452cde1a7f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5874
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Register xPSR is indexed directly with its value 16 or with the
incorrect enum ARMV7M_xPSR.
Replace them with the new enum ARMV7M_REGSEL_xPSR.
Change-Id: I86600e7f78e39002ce45f66d4792d5067c1f541b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5873
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Old stlink firmware in stlink V1 and stlink V2 pre-J15 do not
handle FPU registers in the read_reg() and write_reg() API.
Add code to be compatible with the new API of OpenOCD.
Change-Id: Ib0439c5294b6911ea75efe8c7fa085b014317a4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5883
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The API of hla have been defined from ST-Link basic operations.
By chance, all the current implementation of hla (st-link, ti-icdi
and nulink) share the same way to handle the parameter 'num' of
the API read_reg() and write_reg(), that is simply using it to
initialize the field REGSEL (bits [6:0]) of armv7m Debug Core
Register Selector Register (DCRSR).
Add a comment in the API definition to highlight this, in case it
get used by a further hla implementation, then rename as 'regsel'
the 'num' parameter.
Change-Id: I4b6a2c7d78b4fc4de2b9b2bdba065414b15c6ba3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5882
Reviewed-by: Edward Fewell <edwardfewell@hotmail.com>
Tested-by: jenkins
Reviewed-by: Zale Yu
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Consolidate low level register read/write.
Floating point registers were handled by target_read/write_u32
unlike other registers handled by cortexm_dap_read/write_coreregister_u32
There is no reason to do so in cortex_m.
Remove cortexm_dap_read/write_coreregister_u32
and use cortex_m_load/store_core_reg_u32 directly.
Similarly HLA adapters register read/write interface supports all registers
so use it for any floating point and other registers.
Change-Id: Ida679e5f4fec02d94ffb0bd3f265ed7ed2221cdc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5864
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move primask/basepri/faultmask/control packing/unpacking from
cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg()
and armv7m_write_core_reg() where also the FP 32/64-bit registers
conversion takes place.
Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL
for packing/unpacking of special registers in the register cache.
The new packing/unpacking is endianess safe.
While on it improve returned error codes and LOG_ messages.
Just minimal changes in cortex_m.c and hla_target.c, will be
consolidated in the next patch.
Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5863
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Make arm register id coherent with reg_list index.
Without this reg_list[ARMV7M_R12] was possible but
reg_list[ARMV7M_FPSCR] was out of bounds.
Remove unused items from reg_list index.
Change-Id: I84d3b5c496fc1839d07a5b74cb1fd1c3d4ff8989
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5862
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Define a new enum with DCRSR.REGSEL selectors.
Introduce armv7m_map_id_to_regsel() to unify mapping in one place.
Use DCRSR.REGSEL selectors for low level register read/write.
Change-Id: Ida0ccdfa9cdb1257a1900b8bfbf172b076374d39
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5327
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Introduce a 'hidden' flag in struct reg to support a register cache
containing different views of same data: e.g. Cortex-M has
primask, basepri, faultmask and control registers accessed
as one word. With the hidden flag we can add an reg_list item
corresponding to hw access without exposing the register to user level.
All the struct reg are allocated with calloc() but one in xscale.c
allocated by malloc(). Change this one to use calloc() as well
to guarantee initial value hidden=false
Change-Id: I8da9f5a5a60777ae7ef943a841307487bd80fc6f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5325
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add space around operators;
use BIT() macro in place of left shifting constant 1;
remove space between cast operator and value;
do not check a pointer before free() it;
add parenthesis around parameters in macros;
fix indentation using only TABs;
remove line continuation '\' at code lines out of macros.
Change-Id: I809e8ee72d7bfe49d0edf10afb36efe2458de77c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e44539d66c ("Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface")
Reviewed-on: http://openocd.zylin.com/5932
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Use the board file name as <company>_<name>.cfg
Add the SPDX tag to workaround an error in checkpatch that fails
to recognize as valid a patch that only changes a file name.
Change-Id: I929cd9e5f9fe2e7386950643487534c9a5a05bc6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e44539d66c ("Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface")
Reviewed-on: http://openocd.zylin.com/5931
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
When the core is in sleep mode, the core is no longer retiring
instructions. Cortext M remains in "unknown" state. This patch converts
sleep mode to "running" state.
Change-Id: I1e9b6c9be51fd0f1f6ce81af9b1f5f9f1f43c661
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: http://openocd.zylin.com/5921
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
- write speed up to 150 kByte/s on STM32F469I-disco (due to
SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
(tested only in single/quad mode as most devices either don't
support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
(superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
and single 8-line modes, (not in hyper flash mode)
Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.
Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
Use integer rounding for the computation of prescaler.
Improve the test of prescaler range, knowing its value would be
decremented before being written in TPIU ACPR.
Change-Id: I041dde1dca41323904e36a6b6975028a6de902b3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5909
Tested-by: jenkins
While stlink v2 anly accept till to 2 MHz for SWV baudrate, stlink
v3 accepts up to 24 MHz.
Check the stlink version and use the respective max value.
Change-Id: I911207a35983b6acf0b901059076dd31f70e6290
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Pawel <phryniszak@users.sourceforge.net>
Fixes: https://sourceforge.net/p/openocd/tickets/283/
Reviewed-on: http://openocd.zylin.com/5908
Tested-by: jenkins
The value stored in TPIU ACPR is the prescaler value decremented
by one. Thus, the test should verify that prescaler does not
exceed the maximum ACPR value plus one. Also, zero value is not
allowed for prescaler.
Change-Id: I1817f04f2a310b2f413bad726f0cb9dd6a4172e2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5907
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
Commit 462c012066 ("Add complete JTAG debug logging.") breaks
the build for minidriver, that is enabled either on zy1000 build
and on minidriver-dummy build. The check on BUILD_ZY1000 was added
to pass the auto-build in jenkins. While the build issue with
minidriver-dummy was known, as reported in the comment, it was not
addressed and got ignored for slightly more than one year.
Use the macro HAVE_JTAG_MINIDRIVER_H in place of BUILD_ZY1000 to
take in account both builds that require the minidriver.
Fix also the build in case configure enables the HLA drivers due
to autodetection of libusb. The HLA drivers would not be in the
build and the function transport_is_hla() would be missing.
Change-Id: I1d85c5fa247bf4a85aba29b233c0b573b46665bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5911
Tested-by: jenkins
The function arm7tdmi_clock_out() has one unused 'deprecated'
parameter.
Drop the unused 'deprecated' parameter and the FIXME above it.
Change-Id: Ia8de41f5b8258825faccc737bba622e44c81a7ea
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5912
Tested-by: jenkins
The only code dealing with tftp in OpenOCD was in eCos build, code
already dropped in commit 39650e2273 ("ecosboard: delete
bit-rotted eCos code") almost 8 years ago.
Drop tftp related documentation too.
Change-Id: I0defc8f844e74c90894dca04a652dcc497a520e1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5913
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Jimtcl 0.80 (2020-10-29) adds dependency to libutil, which is part
of the GNU libc.
The library is searched and used by jimtcl build, but still has to
be linked in by OpenOCD as indirect dependency.
While OpenOCD is still using jimtcl 0.79, let's prepare to switch
to the next version.
Add libutil search in configure.ac.
Change-Id: I5a8952161b0e5b93fc00d23be256b5274d31e08c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5922
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
regsub doesn't work correctly on macOS Catalina, which results in
an incorrect CHIPNAME derived from the current target. Since regsub
is only used by this target, replace it with a simple string search
for '.' followed by a substring. This is funcionally equivalent to
what the regular expression was doing, but instead relies in simpler
string operations that should have little to no differences
between systems.
Also, refactor CHIPNAME detection into proc stm32h7x_chipname, so
it's always retrieved in the same way without duplicating the code.
Change-Id: Ia9f63f56b508688e74278b022eaec47e503916e7
Signed-off-by: Alberto Garcia Hierro <alberto@garciahierro.com>
Reviewed-on: http://openocd.zylin.com/5872
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
When a target examination fails, continue to examine subsequent targets.
Return the number of targets that failed to examine.
Change-Id: I883a0c445edc7eb00f496b79271d773771ec6b66
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: http://openocd.zylin.com/5855
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
While at it, fix some coding style issues.
Change-Id: Id521394d89e0bf787a6f812701c2cc0fe7e4e63f
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5919
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
According the CVE-2020-15228 documented in:
- https://github.com/advisories/GHSA-mfwh-5m23-j46w
- https://nvd.nist.gov/vuln/detail/CVE-2020-15228
the `set-env` commands will be disabled in the near future
and should be replaced by:
echo "FOO=BAR" >> $GITHUB_ENV
idem for `add-path`, should be replaced by:
echo "/path/to/add" >> $GITHUB_PATH
Change-Id: I725c9ccd861a0d1580ac22491b6d716ec65973d1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5866
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
When trace capturing the trace is enabled using 'tpiu_config internal'
(via the internal mode), OpenOCD can collect the trace buffers then append
it to a specified file or named pipe and propagate the trace to 'tcl_trace'
command.
This change is allowing OpenOCD to stream the captured trace over TCP.
When using this configuration OpenOCD acts like a server and multiple
clients can connect and receive the captured trace.
Example on STM32F7 running at 216MHz:
itm port 0 on
tpiu config internal :3344 uart off 216000000
Change-Id: Idea43e7e26e87b98a33da7fb9acf7ea50fe3b345
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5345
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Antonio Borneo
Boran Car
Marc Schink
Tomas Vanek
Tarek BOCHKATI
Tarek BOCHKATI
Mickaël Thomas
Kevin Yang
Andreas Bolsch
Alberto García Hierro
Jonathan McDowell
Adrian Negreanu