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8006 Commits

Author SHA1 Message Date
Tim Newsome bb2c25c5ce Make OpenOCD work when there is no program buffer. 
Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.

Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
 2018-01-31 15:33:45 -08:00
Tim Newsome ee93a9b2f1 Add error handling code to system bus read/write 
It's not tested because spike never reports any busy errors since every
access happens instantaneously.

Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
 2018-01-30 08:53:46 -08:00
Tim Newsome 0f0c5b1ff5 Merge branch 'riscv' into sysbusbits 
Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
 2018-01-29 11:39:14 -08:00
Tim Newsome ec543bdc7b
Merge pull request #198 from riscv/hartsellen 
Detect hartsellen, limiting which harts we probe
 2018-01-29 11:11:00 -08:00
Tim Newsome 6a98fb7076 Detect hartsellen, limiting which harts we probe 
Tested with doctored spike with hartsellens of 0, 1, 3, and 10.

Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
 2018-01-26 16:39:58 -08:00
Tim Newsome 5184c32125 Clear errors that we see. 
Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...

Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
 2018-01-26 15:43:05 -08:00
Tim Newsome b67379700b Add support for v1 system bus access. 
This is functional, but doesn't handle errors.

Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
 2018-01-26 15:43:05 -08:00
Tim Newsome beac00149c Use new debug_defines.h 
Change-Id: Iefc8424343dbed05fa9dacc626829955fc16f299
 2018-01-26 15:41:45 -08:00
Tim Newsome 68c57474f9
Merge pull request #192 from riscv/memlog 
Make all memory logging lines consistent.
 2018-01-25 10:51:35 -08:00
Tim Newsome 2d263bae84 Make all memory logging lines consistent. 
Also reduce a few 64-bit variables to 32 bits, which is all they need.

Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
 2018-01-24 13:53:11 -08:00
Tim Newsome 42e601afc1
Merge pull request #191 from riscv/scanbuild 
Fix some niggles found by clang's static analysis.
 2018-01-24 07:59:47 -08:00
Tim Newsome 553a63808c Fix some niggles found by clang's static analysis. 
Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
 2018-01-23 15:16:23 -08:00
Megan Wachs 5e22040b67
SPI Flash: add 256Mb SPI Part by ISSI 2018-01-20 13:34:53 -08:00
Tim Newsome 5ea8bb90df
Merge pull request #189 from riscv/examine_err 
Add some error checking to examine().
 2018-01-19 17:06:34 -08:00
Tim Newsome 446044db89
Merge pull request #187 from riscv/fespi 
Make compilation command specify architecture.
 2018-01-19 16:28:02 -08:00
Tim Newsome 3839cbf0ad Add some error checking to examine(). 
Fixes #183.

Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
 2018-01-19 13:58:02 -08:00
Tim Newsome 1ab7e910fd Make compilation command specify architecture. 
Fixes issue #180.

Change-Id: Icf180ae87db92840930044f1aa3129466cf43fad
 2018-01-19 11:41:17 -08:00
Tim Newsome cb543e804d
Merge pull request #184 from riscv/cleanup 
Remove dead code.
 2018-01-17 15:08:30 -08:00
Tim Newsome 7f368468c8 Remove dead code. 
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
 2018-01-15 12:07:20 -08:00
Megan Wachs 6f9585068f
Merge pull request #172 from riscv/dbus_read_comment 
Add a comment in dbus_read
 2018-01-10 15:30:56 -08:00
Tim Newsome 0d60a29c21
Merge pull request #178 from riscv/cleanup 
Rename dummy variable to be correct.
 2018-01-10 15:16:40 -08:00
Tim Newsome 160b794274
Merge pull request #181 from riscv/propagate_errors 
Propagate register read errors
 2018-01-10 15:16:19 -08:00
Tim Newsome 29c7a76708 Muck with mstatus to always be able to read FPRs 
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
 2018-01-09 12:06:11 -08:00
Tim Newsome fd506fa839 Propagate register read errors. 
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
 2018-01-08 11:53:02 -08:00
Tim Newsome 0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection 
Select current hart before reading memory.
 2018-01-05 14:07:38 -08:00
Tim Newsome 11e51af3b1
Merge pull request #173 from riscv/warn_names 
Use register names instead of numbers in warnings
 2018-01-05 13:07:08 -08:00
Tim Newsome 37434ffd77 Rename dummy variable to be correct. 
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
 2018-01-05 13:05:33 -08:00
Tim Newsome a6b503217d
Merge pull request #174 from riscv/delay_info 
Make delay update messages debug instead of info.
 2018-01-05 13:03:14 -08:00
Tim Newsome 6f3913cedc Select current hart before reading memory. 
This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).

Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
 2018-01-04 17:12:01 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info. 
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
 2018-01-04 13:36:53 -08:00
Megan Wachs 33aad3524b
Add a comment in dbus_read 
This just comments the current behavior
 2018-01-04 13:27:35 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings 
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
 2018-01-04 13:27:18 -08:00
Tim Newsome 82529e71e0
Merge pull request #170 from riscv/strtoull 
Parse 64-bit CRC addrs even on 32-bit hosts
 2018-01-03 12:48:36 -08:00
Tim Newsome 2eddd8e092 Parse 64-bit CRC addrs even on 32-bit hosts 
Change-Id: I38720163eff292b2c24f25da4e25feb8245ff672
 2018-01-02 12:58:46 -08:00
Tim Newsome f822956994
Merge pull request #169 from riscv/unused_boards 
Remove board files that I shouldn't have added
 2018-01-02 12:19:55 -08:00
Tim Newsome 1ddbe70443 Remove board files that I shouldn't have added 
There are 3 other ones for the SiFive target.

Change-Id: I987331a82186a3738096cc390c91889118bf9ac2
 2017-12-29 13:11:27 -08:00
Tim Newsome ab5a98663e
Merge pull request #168 from gnu-mcu-eclipse/sifive-cfg 
Add config files for the SiFive boards
 2017-12-29 11:39:57 -08:00
Liviu Ionescu bd566a98bc add configs for the SiFive boards 
- the HiFive1 board definition includes the FTDI interface
- the Arty boards require external interface definitions
 2017-12-29 17:36:54 +02:00
Tim Newsome 603ed9c419
Merge pull request #167 from riscv/sifive_cfg 
Add config files for SiFive RISC-V hardware.
 2017-12-28 16:34:57 -08:00
Tim Newsome c27a777eb8
Merge pull request #165 from riscv/typo 
Fix typo.
 2017-12-28 16:13:11 -08:00
Tim Newsome 8150358cde Add config files for SiFive RISC-V hardware. 
Copied from https://github.com/gnu-mcu-eclipse/openocd

Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
 2017-12-28 16:10:41 -08:00
Tim Newsome 52368d6ea1 Fix typo. 
Issue #164

Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
 2017-12-28 11:52:59 -08:00
Tim Newsome 0774011e21
Merge pull request #163 from riscv/no_abort 
Get rid of abort() calls.
 2017-12-27 14:01:46 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls. 
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
 2017-12-27 13:45:50 -08:00
Tim Newsome d7ed191457
Merge pull request #162 from riscv/no_abort 
Propagate error instead of calling abort().
 2017-12-27 10:00:59 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort(). 
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
 2017-12-26 15:04:02 -08:00
Tim Newsome ca700dcef0
Merge pull request #161 from riscv/dead_code 
Remove unused code.
 2017-12-26 14:54:00 -08:00
Tim Newsome 4fa3d819d2 Remove unused code. 
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
 2017-12-26 14:27:44 -08:00
Tim Newsome 561b0c94c0
Merge pull request #160 from riscv/style 
Conform to OpenOCD style guide.
 2017-12-26 14:01:54 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide. 
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
 2017-12-26 11:38:11 -08:00