interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Make compilation command specify architecture. 

Fixes issue #180.

Change-Id: Icf180ae87db92840930044f1aa3129466cf43fad
This commit is contained in:
Tim Newsome 2018-01-19 11:41:17 -08:00
parent cb543e804d
commit 1ab7e910fd
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/flash/nor/fespi.c
View File

@ -465,8 +465,9 @@ static int slow_fespi_write_buffer(struct flash_bank *bank,
* Here's the source for the algorithm.
* You can turn it into the array below using:
sed -n '/ALGO_START$/,/ALGO_END/ p' fespi.c | \
riscv32-unknown-elf-gcc -x assembler-with-cpp - -nostdlib -nostartfiles -o tmp.o && \
riscv32-unknown-elf-objcopy -O binary tmp.o algorithm.bin && \
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -x \
assembler-with-cpp - -nostdlib -nostartfiles -o tmp.o && \
riscv64-unknown-elf-objcopy -O binary tmp.o algorithm.bin && \
xxd -i algorithm.bin
// ALGO_START