Commit Graph

544 Commits

Author SHA1 Message Date
liangzhen a8ffda6e70 target/riscv: support riscv repeat_read by sysbus access
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-09-21 15:33:17 +08:00
Tim Newsome 5efea16944
Merge pull request #900 from aap-sc/aap-sc/simplify_state_managment
riscv: simplify state management during examine
2023-08-29 10:11:52 -07:00
Tim Newsome 7aedb15951
Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_running
fix crash when we try to read vector register on a running target
2023-08-23 12:01:49 -07:00
Tim Newsome 5cb60e3f7d
Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
2023-08-18 09:32:51 -07:00
Parshintsev Anatoly 198edca6d0 riscv: simplify state management during examine
This also fixes a bug when, after `examine` completion, the target still
has  `unknown` status. To reproduce this one spike, it is enough to do
the following:

---
// make sure spike harts are halted
openocd ... -c init -c 'echo "[targets]"'
---

this behavior is quite dangerous and leads to segfaults in some cases

Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 15:29:19 +03:00
Parshintsev Anatoly 0ae47ae472 fix crash when we try to read vector register on a running target
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 00:18:10 +03:00
Xiang W 373b8f1a89 target/riscv: fix execute_fence
This patch improves the following issues:
1. Makes it compatible with targets with progbufsize == 1.
2. Although exceptions don’t update any registers, but  do end execution
of the progbuf. This will make fence rw, rw impossible to execute.

Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6
Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-17 09:05:36 +08:00
Parshintsev Anatoly a8fedebcb4 [riscv] refactor functions that register read/write via progbuf
The motivation for this refactor is to fixup error handling for some
corner cases. These functions attempt to cache S0 register and only then
perform a bunch of extra checks to figure out if the requested register
is valid one in this context. The problem is that there are few corner
cases when _*progbuf functions could receive a GPR as an input. For
example, an abstract read could fail (for whatever reason) leading to
infinite recursion:

````
save S0 -> read S0 -> save S0 -> read S0 -> ...
```

The case described above could be fixed by adding extra sanitity checks,
however I decided to make these functions more modular since I find
self-contained functions easier to read.

Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-15 17:54:00 +03:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Tim Newsome 814a3b5e7b
Merge pull request #871 from en-sc/en-sc/fix-mdx-err
target/riscv: refactor read_memory_progbuf()
2023-07-17 09:30:11 -07:00
Evgeniy Naydanov 8d660ea98d target/riscv: refactor read_memory_progbuf()
There were a couple of problems with previous implementation:

* Misalligned read would return ERROR_OK and print all zeroes.

* CMDERR_BUSY for abstract access was improperly handled:

According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.

* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.

Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-14 22:23:02 +03:00
Mark Zhuang d5425c253c target/riscv: dynamic allocate memory for hawindow
Change-Id: Id2f1a2568a39eec0a9dd4fe0f155619b11f9d6ba
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:47 +08:00
Mark Zhuang 34418ed1c8 target/riscv: fix haltgroup_supported to info->haltgroup_supported
Change-Id: Id1276aecd3097d90e035bf3808e0c472188ba474
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-06-27 15:46:23 +08:00
Tim Newsome 470c2a402c
Merge pull request #868 from en-sc/en-sc/upstream-resume-err-2
target/riscv: resume only halted harts
2023-06-21 09:37:40 -07:00
Evgeniy Naydanov 8ca5c2fbe4 target/riscv: resume only halted harts
With this change, failures to resume a hart due to it not being halted
are more explicitly logged or reported as an error.

Change-Id: Ia55d8df85a908363d0f2140637ce1e47c1ab6251
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-06-21 11:44:38 +03:00
Tim Newsome bf07ddef8a target/riscv: From tick(), set ebreak* if necessary.
This involves halting the target, which might have unintended side
effects, but when the debugger is connected software breakpoints must
trap to the debugger. Anything else is a terrible user experience.

Change-Id: I1f7bb610eeeb054cc3042dc6bcfc16589ce12a31
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:59:45 -07:00
Tim Newsome da5bf318b9 target/riscv: Track whether ebreak* is set.
We need to know, so we can set it when necessary.

Change-Id: I1f0d5107f1208f7b9316e15870f0804e51232dee
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:49 -07:00
Tim Newsome 6e64b685f4 target/riscv: Track whether halt groups are supported.
Will be used later when we want to do a quick halt/resume.

Change-Id: Ib80166234c4c277b7d9ce26b7566ac0f93017e64
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:31 -07:00
Tim Newsome b496bebcda target/riscv: Improve update_dcsr()->set_dcsr_ebreak()
* Only set ebreak bits that might be supported based on misa.
* Don't write dcsr if its value wouldn't change.

Change-Id: I7087af0b0df0fbdbf994373b5c887b9b389df872
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 9d8bbb559d target/riscv: Tweak set_group().
Make it callable earlier, handle `supported` being NULL, and make enum
names more clear.

Change-Id: If4d286b54ccfc01eb5de5a57eb18f748c920e979
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 866282ba9e target/riscv: Add debug msg to reset_delays_wait
Makes it easier when reading debug logs.

Change-Id: I3938437357e0d74e1cda680693f907a20c5579c7
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 2a64da39b0 target/riscv: Remove unused riscv013_on_halt function
The riscv013_on_halt function was being called but its implementation was
empty, providing no additional functionality. Removed the function declaration,
calls to it, and its implementation since it is not required.

Change-Id: I425ea890deadeec945f0a47af247f3f99172e801
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome ad89d570e7 target/riscv: set_dcsr_ebreak() while target->state is still changed
Otherwise it fails.

Fixes #859.

Change-Id: Ib59e6d840316b881481a9b1e01f9d546e73bf932
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-07 09:49:58 -07:00
Tim Newsome 0ab2ebd191 target/riscv: Select hart in update_dcsr()
Otherwise we may end up modifying DCSR of a different hart than
intended.

Change-Id: I39bde21a1444623ed150f2b3d504b9318b9d6191
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-05 09:39:14 -07:00
Tim Newsome 5a9654d272
Merge pull request #854 from en-sc/en-sc/fix-regacc-running
target/riscv: fix register access on running target
2023-06-02 08:25:07 -07:00
Evgeniy Naydanov 3a29542056 target/riscv: fix register access on running target
Register access on running target should fail if mstatus needs to be
modified.

Change-Id: Iec8e8d514ef2f5ca42606a5534cce55aaaa99180
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-31 22:22:53 +03:00
Tim Newsome f0898155d1 target/riscv: Set dcsr.ebreak* during examine()
This way if you connect to a running target, before it's hit a breakpoint,
then when it does hit the breakpoint OpenOCD will catch it.

Change-Id: I6f1e5f169fa385f46759015786e664693c3872e4
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:01:47 -07:00
Tim Newsome 21433e83ee target: poll() failure does not mean the target halted.
Poll failure just means poll failed. It's safer to assume the target is
still running, because then if it is running and subsequently halts we can
relay this to gdb correctly. We can't do the other way around, because once
gdb thinks the target has halted, it can't deal with it spontaneously
running.

Change-Id: Idb56137f1d6baa9afc1b0e55e4a48f407b8ebe83
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 82ed02f92a target/riscv: Always clear progbuf cache in examine().
When a DM was powered down, we end up in examine() again, and clearly if
the DM was powered down we need to invalidate that cache.

Change-Id: I5eb6a289939f313e06c09cac22245db083026aa3
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 1c5cf8023c target/riscv: Reset DTM when it reports an error.
The error state is sticky, so this has to be done to recover.

Change-Id: I589f3cdab0f2351fd25f89951830cbc16c39bd93
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Evgeniy Naydanov 5a29a7399f target/riscv: refactor register accesses
Change-Id: I45731d501f6261c4142c70afacf3fbbe42cf2806
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-23 20:20:19 +03:00
Evgeniy Naydanov c822dc8194 target/riscv: improve register caching (prep_*, cleanup_*)
Introduce riscv_write_register to prep_for_register/vector_access and
cleanup_after_register/vector_access.

Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 7a181e8bbc target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently
Change-Id: Ia476251e835fa5fd129ae6b679c6049c5c60c716
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Tim Newsome be5187d0a8 target/riscv: Comment that data1 might change.
In case in the future I have the same idea of optimizing progbuf writes
again.

Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-17 09:46:23 -07:00
Parshintsev Anatoly 7ca8350d3a target/riscv: respect error code from dm013_select_target in select_prepped_harts
Change-Id: I3099589521538590e366d60629e49cfc74e2d0c6
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-04-24 21:15:56 +03:00
Mark Zhuang aa7344225b target/riscv: support log memory access128 for read
Change-Id: I9235150fa00c03a1d75d0b44a7500758daa56e2b
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-10 09:48:48 +08:00
Tim Newsome 15bb3e23b8
Merge pull request #821 from en-sc/en-sc/fix-reset-mharts
target/riscv: simplify reset for rtos harts
2023-04-06 09:54:15 -07:00
Tim Newsome 7e36bb6158
Merge branch 'riscv' into hypervisor
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-05 10:48:56 -07:00
Evgeniy Naydanov 1c168242e9 target/riscv: simplify reset
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
2023-04-05 19:14:45 +03:00
Tim Newsome c6ba4166e4
Merge pull request #816 from riscv/from_upstream
Merge up to commit '1293ddd65713d6551775b67169387622ada477c1' from upstream
2023-04-05 08:47:27 -07:00
Tim Newsome 4fdcc14e26 target/riscv: Set hypervisor bits.
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?

Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-29 13:40:39 -07:00
Mark Zhuang dfce1d2708 target/riscv: [NFC] rename variables named read/write
read/write is system function

Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 21:18:12 +08:00
Mark Zhuang 4cccda353c target/riscv: support log memory access128
Change-Id: I6b22c97f81fac26703b66d3dbd8b6d41aaea4875
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 20:31:42 +08:00
Tim Newsome 868ebdd89c Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.

Conflicts:
	.travis.yml
	contrib/loaders/flash/stm32/stm32f1x.S
	contrib/loaders/flash/stm32/stm32f2x.S
	doc/openocd.texi
	src/rtos/FreeRTOS.c
	src/server/gdb_server.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg
	tcl/target/gd32vf103.cfg
	tools/scripts/checkpatch.pl

Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2023-03-16 18:02:35 -07:00
Tim Newsome 2c760b6317 Expose S?aia CSRs if they're on the target.
Untested, because I don't have a target that implements this.

Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16 15:37:06 -07:00