Commit Graph

350 Commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD d6027ca6a8 at91: add at91sam9263 chip register definition
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-04-09 19:19:36 +02:00
Jean-Christophe PLAGNIOL-VILLARD ba71e8c521 at91: add chip register definition and generic init support
for
 - pio
 - pmc
 - rstc
 - wdt
 - sdramc
 - smc

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-04-09 19:18:03 +02:00
Jean-Christophe PLAGNIOL-VILLARD 28e6dcee85 add at91sam9263-ek support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-04-09 10:16:28 +02:00
Jean-Christophe PLAGNIOL-VILLARD 22437fac28 add at91sam9261-ek support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-04-09 10:14:46 +02:00
Jean-Christophe PLAGNIOL-VILLARD 5d538084be at91: add at91sam9261 chip register definition
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-04-09 10:13:59 +02:00
Øyvind Harboe 3fea99097e pandaboard: use new -dbgbase option to workaround broken ROM table
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-04-02 09:00:01 +02:00
Øyvind Harboe 6c5e1781a1 omap4430: cortex a9 and a8 are now merged again
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-03-22 09:10:21 +01:00
Aaron Carroll 59a6380a17 omap4430: add Blaze config
Signed-off-by: Aaron Carroll <aaronc@ok-labs.com>
2011-03-13 14:59:39 +01:00
Aaron Carroll cc9939879c omap4430: force hardware breakpoints for GDB
Soft breakpoints are currently broken if the MMU is enabled due to incorrect
cache flushing.  Until this is fixed, force the use of hardware breakpoints.

Signed-off-by: Aaron Carroll <aaronc@ok-labs.com>
2011-03-13 14:58:57 +01:00
Jean-Christophe PLAGNIOL-VILLARD df500c5a04 at91: add at91sam9g45 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-03-03 22:49:47 +01:00
Jean-Christophe PLAGNIOL-VILLARD a4bf71386b at91: add at91sam9g10 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-03-03 22:49:47 +01:00
Jean-Christophe PLAGNIOL-VILLARD aebc0d5556 at91sam9260: update sram information
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-03-03 22:49:47 +01:00
Jean-Christophe PLAGNIOL-VILLARD f6783d4465 at91: add at91sam9263 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-03-03 22:49:47 +01:00
Jean-Christophe PLAGNIOL-VILLARD 26db0a6bef at91: add at91sam9261 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-03-03 22:49:46 +01:00
Jean-Christophe PLAGNIOL-VILLARD e941805713 at91sam9: factorise cpu support
all at91sam9 are nearly the same except sram and soc name

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-03-03 22:49:46 +01:00
Jean-Christophe PLAGNIOL-VILLARD f26cd96740 add at91rm9200-ek board support
tested with jlink sam-ice v5 while loading barebox

(gdb) load
Loading section .text, size 0x2f190 lma 0x21f00000
Loading section .rodata, size 0x931c lma 0x21f2f190
Loading section .data, size 0x29e8 lma 0x21f384ac
Loading section .barebox_cmd, size 0x78c lma 0x21f3ae94
Loading section .barebox_initcalls, size 0x80 lma 0x21f3b620
Start address 0x21f00000, load size 243360
Transfer rate: 26 KB/sec, 13520 bytes/write.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-02-23 08:13:59 +01:00
Luca Ellero 578294dbdd stm32: add ID for medium density device Rev Z
stm32-discovery evaluation board (STM32F100RBTB6):
reading device id register (0xE0042000) returns 0x10010420

Signed-off-by: Luca Ellero <lroluk@gmail.com>
2011-02-18 08:08:31 +01:00
Luca Ellero 6684b35346 omap4430: Add JRC TAPID for PandaBoard REV EA1 (PEAP platforms)
PandaBoard REV EA1 (Panda Early Adopter Program) has a different ID.
This patch add alternate REV EA1 TAP id to configuration file

Signed-off-by: Luca Ellero <lroluk@gmail.com>
2011-02-08 09:51:54 +01:00
Aaron Carroll aaf145c422 omap4430: fix reset sequence
* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
  takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.

Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
2011-02-02 08:32:10 +01:00
Aaron Carroll 4592506b8e TCL configs for OMAP4430 and Pandaboard
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
2011-01-31 08:57:50 +01:00
Mathias K 6df10184f6 - add xds100v2 configuaration file
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2011-01-27 10:32:39 +00:00
Freddie Chopin 61e1e525c1 Add another level of procedures to LPC2xxx initialization - procedures for specific targets (setup_lpc<number>) take core clock and adapter clock as parameters. This way "constant" parameters (flash size and type, CPUTAPID, etc.) do not need to be copied if one wishes to change the "variable" parameters - like the core clock or adapter clock - in a board config file or somewhere else.
Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
2011-01-09 21:34:02 +01:00
Freddie Chopin 94fa8fd30a Add common LPC2xxx setup procedure, use in all LPC2xxx files.
Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
2011-01-07 16:09:31 +01:00
Michael Schwingen 1795239cfd actux3.cfg: add function to setup for u-boot debugging
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-01-02 21:17:57 +01:00
Spencer Oliver 3d834bdab7 stm32: add stm32 xl family flash support
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-12-23 12:11:14 +00:00
Øyvind Harboe 8b41812da3 lpc2148: redo to the new target configuration scheme
Define a proc which PCBs can easily override.

Also demonstrates how to add multiple TAP exepcted-id's
using arguments.

Added 0x3f0f0f0f as expected TAP-id. Old LPC2148 silicon
I happened to have on my desk?

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-12-22 17:44:22 +01:00
Tormod Volden 29d2d15f3f tcl/interface/flashlink.cfg: Fix broken ST URL 2010-12-20 07:52:29 +01:00
Tormod Volden d33f4a2ad5 tcl/board: Clean up STM32 EVAL boards configurations
Make consistent use of hex memory size for flashing.

Delete stm32f10x_128k_eval.cfg. It has no product reference
nor any settings in it.
2010-12-20 07:52:28 +01:00
Tormod Volden 9f18afc39e tcl/board: Fix ST URLs in stm32* eval board configuration files
ST recently rewamped (screwed up) their web site and broke all links.
Also match the chip names with those on the web site product
descriptions.
2010-12-20 07:52:26 +01:00
Michael Schwingen 23bf724e04 update IXP42x target / XBA board config 2010-12-19 22:16:31 +01:00
Michael Trensch 6839618062 Add support for Hilscher netX controllers 2010-12-18 21:11:57 +01:00
Antonio Borneo 30da7c67ce TCL: fix non TCL comments
End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-12-18 21:04:22 +01:00
Spencer Oliver c6e07051e6 stm32: add STM32E-EVAL external memory config script
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-12-10 13:36:10 +00:00
Freddie Chopin 4bd2b30d5b remove srst_pulls_trst from LPC2xxx target scripts
LPC2xxx do not require reset_config srst_pulls_trst. This can cause various "strange" problems when flashing the chip, because "reset halt" actually allows the chip to run for some short period of time and execute some code.

Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
2010-12-09 22:54:31 +01:00
Rolf Meeser 6ef4e97779 lpc2478 target config: CCLK as (mandatory) parameter 2010-12-05 13:37:57 +01:00
Rolf Meeser 81790fb56a Add board config for Embedded Artists LPC2478-32 2010-12-04 09:36:47 +01:00
Rolf Meeser bd9d2468cb Fix flash name in Hitex LPC2929 board config 2010-12-04 09:36:17 +01:00
Spencer Oliver 0ac6c0d1a8 stm32: set default soft reset config
If no srst is configured then default to using sysresetreq to
reset the target.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-12-03 09:02:10 +00:00
Spencer Oliver 7b2687b45b luminary: remove unused config cmds.
Due to commit e40aee2954d2beabe1d8c530d9ff1e564fb01f48 we now honour the
targets 'reset_config' setting. Previously we ignored the srst setting
for luminary targets.

Luminary targets have never supported using srst to reset into debug mode
so remove the option from the target configs files.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-12-03 09:02:08 +00:00
Spencer Oliver c24087d33e config: fix luminary jtag config
When this config was updated in commit e3773e3e3d
the old jtag declaration was not removed.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-12-02 22:01:44 +00:00
Freddie Chopin a1ce28b118 rename some target scripts to be consistent with the rest
Rename Atmel target scripts which had wrong name ("at91" missing for ARM7 AT91SAM7..., "at" missing for AVR ATmega...)

Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
2010-12-02 18:53:03 +01:00
Piotr Esden-Tempski 94e1445a86 Added support for the blinking leds on Floss-JTAG v0.3 and newer. 2010-11-30 08:15:19 +01:00
Piotr Esden-Tempski a9d0b3de44 Updated Floss-JTAG config file to support v0.3 and newer. Also added noeeprom version of the config file for older versions of Floss-JTAG. 2010-11-30 08:15:19 +01:00
Antonio Borneo 42082f7c23 FLASH/NOR: rename from spearsmi to stmsmi
STMicroelectronics controller SMI is not SPEAr specific.
Rename it and change name to every symbol in the code.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-11-23 08:37:34 +01:00
Antonio Borneo 4bbdf966d4 STR750: Add SMI interface support
Modified spearsmi driver to include support for STR75x
Added missing initialization in tcl file for STR750

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-11-23 08:37:31 +01:00
Antonio Borneo 09c798a144 TCL/SPEAr: Added Serial flash in board file
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-11-16 09:16:15 +01:00
Antonio Borneo e7b2958229 TCL scripts: replace "puts" with "echo"
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-11-09 08:12:51 +01:00
Andrew Leech fc4cbc0f98 lpc3131: target definition 2010-11-09 08:05:55 +01:00
Antonio Borneo 074498f836 TCL scripts: add support for ST SPEAr310
Initial support for ST SPEAr310 and for the evaluation
board EVALSPEAr310 Rev. 2.0.
Scripts are split in generic for SPEAr3xx family and
specific for SPEAr310. This should easily allow adding
new members of the family.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-11-06 15:40:52 +01:00
Marek Vasut 8f1f8e7b96 Add EfikaMX smarttop board support
This patch finally adds support for i.MX51 based Genesi USA EfikaMX smarttop
board.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-11-05 11:25:57 +01:00
Marek Vasut d5b9c7998c CortexA8: Introduce Freescale i.MX51 variant
This patch introduces support for Cortex A8 based Freescale i.MX51 CPU. This CPU
has the Debug Access Port located at a different address (0x60008000) than TI
OMAP3 series of CPUs.

i.MX51 configuration file based on OMAP3 configuration file and an email from
Alan Carvalho de Assis <acassis@gmail.com>.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-11-05 11:25:57 +01:00
Øyvind Harboe 53228fbc2e imx31pdk: use rclk w/1MHz fallback
measure_clk indicates ca. 3-4MHz, so 1MHz should be safe.

Added self_test proc used to test that rclk worked.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-10-28 08:43:04 +02:00
Peter Stuge f176278e98 Make systesetreq typos read sysresetreq instead
Signed-off-by: Peter Stuge <peter@stuge.se>
2010-10-25 08:05:23 +02:00
Peter Stuge e7d26173fc Remove srst_pulls_trst from LPC1768 target
srst_pulls_trst may be true on some (broken) LPC1768 boards but is
not true in general for the LPC1768.

Signed-off-by: Peter Stuge <peter@stuge.se>
2010-10-25 08:04:58 +02:00
David Brownell e3773e3e3d swj-dp.tcl (SWD infrastructure #1)
Provide new helper proc that can set up either an SWD or JTAG DAP
based on the transport which is in use -- mostly for SWJ-DP.

 Also update some SWJ-DP based chips/targets to use it.  The goal
is making SWD-vs-JTAG transparent in most places.  SWJ-DP based chips
really need this flexible configuration to cope with debug adapters
that support different transports, without needing new target configs
for each transport or adapter.

For JTAG-DP, callers will use "jtag newtap" directly, as today; only
one chip-level transport option exists.

For SW-DP (e.g. LPC1[13]xx or EFM32, they'll use "swd newdap" directly
(part of an upcoming SWD transport patch).  Again, only one transport
option exists, so hard-wiring is appropriate there.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-10-10 14:41:11 -07:00
Antonio Borneo ecad76061f TCL scripts: fix ocd_mem2array/mem2array
In previous patch, I have introduced again the symbol
"ocd_mem2array", now replaced by "mem2array".
Fix the error.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-09-28 10:44:50 +02:00
Zachary T Welch 3bb4a6ba14 Fix omap3_dbginit to write to physical memory.
Setting the OMAP3530 DBGEN bit must be done in physical memory, so
update omap3_dbginit callback to use the new 'mww phys' command syntax.
2010-09-26 17:45:58 -07:00
Antonio Borneo edefee9880 TCL scripts: collect duplicated procedures
TCL procedures mrw and mmw, originally in DaVinci target code,
are duplicated in other TCL scripts.
Moved in a common helper file, and added help/usage description.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-09-21 12:25:59 +02:00
Øyvind Harboe f613011aa0 tcl: remove incomplete unused tcl file
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-09-20 09:23:42 +02:00
Karl Kurbjun 60501bb0fb AM/DM37x: Unify configuration scripts and add support for TI Beagleboard xM. 2010-09-20 09:17:28 +02:00
Takács Áron 1b0f194d90 board scripts: Marvell PXA270M processor has a new TAPID: 0x89265013
the new Marvell PXA270M processor has a new TAPID: 0x89265013.
Attached you will find a patch for target/pxa270.cfg that will handle this.

I have also attached a board/colibri.cfg file to support the Colibri
PXA270 module by Toradex.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-09-14 11:15:35 +02:00
Spencer Oliver 3c69eee9ef cortex m3: add cortex_m3 reset_config cmd
This new cmd adds the ability to choose the Cortex-M3
reset method used.
It defaults to using SRST for reset if available otherwise
it falls back to using NVIC VECTRESET. This is known to work
on all cores.

Move any luminary specific reset handling to the stellaris cfg file.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-08-31 20:09:26 +01:00
Spencer Oliver 31b47688ca cfg: update Luminary config files
- Update all Luminary config's to use a common target/stellaris.cfg.
 - Add Luminary ek-lm3s6965 config.
 - Increase working area for boards with more ram.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-08-31 20:09:24 +01:00
Øyvind Harboe 5c98e063b9 imx35pdk: fix clock and reset delays
Use rclk and 100ms delay on ntrst

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-19 16:06:45 +02:00
Øyvind Harboe 2c4ef30b11 mcb1700: Keil MCB1700 w/1768 config script
Ca. 93kBytes/s flashing speed @ 10MHz JTAG clock

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-17 21:52:39 +02:00
David Brownell 962946ea89 update more Stellaris EK board comments
Using the bundled JTAG/SWD debug support in JTAG mode
is optional on *all* of the EK boards.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-08-16 08:25:37 -04:00
David Brownell 70794664f1 Update comments for some Stellaris EK boards.
These  don't need to use the on-board debuggers in JTAG mode.
Off-board is OK, as would be SWD mode.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-08-16 00:36:52 -04:00
Oleksandr Tymoshenko c54c323cf3 avr32: basic target script 2010-08-15 21:56:41 +02:00
David Brownell d23428a47f at32ap7000 config file
nice board to play with.
2010-08-15 21:54:01 +02:00
Øyvind Harboe f60a2390cc lpc1768: turn down the jtag clock
Tests should that it needs to be as low as 100kHz to be
stable.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-13 12:59:36 +02:00
Piotr Esden-Tempski 52ba344a09 Added Lisa/L script as a target board. 2010-08-13 09:52:31 +02:00
Piotr Esden-Tempski c3ee26d272 Added support for Lisa/L builtin JTAG interface. 2010-08-13 09:52:27 +02:00
Øyvind Harboe a72faf6405 at91cap7a-stk-sdram.cfg: faster reset
crank up JTAG speed as soon as clocks are set up.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-12 15:01:23 +02:00
Thomas Koeller 14a25cd6de DM36x: Set OSCDIV divider
The ability to set up the OSCDIV divider was missing.

Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
2010-08-12 08:59:04 +02:00
Thomas Koeller 4ed89e4e42 DM36x: Disable unused SYSCLKs
Clear the enable bits for all clocks that are not set explicitly.
This is done to increase robustness by removing pre-existing
state.

Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
2010-08-12 08:59:03 +02:00
Thomas Koeller 98d2579c61 DM36x: Use enable bit for PLL pre-divider
The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.

Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
2010-08-12 08:59:02 +02:00
Øyvind Harboe 8f779cf66b tcl: remove silly ocd_ prefix to array2mem and mem2array
ocd_ prefix is used internally in OpenOCD as a kludge more
or less to deal with the two kinds of commands that OpenOCD
has.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-11 17:24:55 +02:00
Øyvind Harboe f1bd1274ee board: added at91cap7a stk w/sdram config scripts
The strange thing here with this board is that 16MHz kinda
works, but only 2MHz is really stable.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-11 17:09:44 +02:00
Øyvind Harboe ba951aede3 config scripts: remove useless reference to OpenOCD docs
clutters config scripts.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-11 10:53:54 +02:00
Ben Gardiner 91305bfa7f cfg: add omapl138 support and da850evm preliminary support
This patch adds support for the omapl138 target and preliminary support for the da850evm. The
target cfg file is based on the icepick routing done by the target/ti_dm6446.cfg file.

I have performed limited testing with this setup. I am posting this patch in the interest of
sharing cfg files and in the hopes that the experts on this list can correct errors I have made or
point out enhancements.

The testing I have performed is debugging uboot with gdb where I also use the following local.cfg
and gdbinit files. Debugging appears to work in so much as 'ni' works.

local.cfg:
gdb_memory_map disable

gdbinit:
target remote localhost:3333
set remote hardware-breakpoint-limit 2
set remote hardware-watchpoint-limit 2
monitor poll on

Comments welcome.

Best Regards,
Ben Gardiner
2010-08-10 09:43:30 +02:00
David Brownell 28ddefd065 Luminary-icdi comment update
Clarify that ICDI is the generic logic, but this config is
for the JTAG-only (no-SWD) mode.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-08-03 21:29:05 -04:00
Øyvind Harboe d1638abd6a lpc1768: even if rclk "works", it isn't necessarily the correct clk
rclk = 4MHz oon lpc1768, the correct JTAG clk is 666MHz(4MHz/6).

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-08-02 13:21:21 +02:00
Peter Stuge 8e9b12dc8a Support NGX Technologies product NGX ARM USB JTAG
This is a standard FT2232 device. More info at their web page:
http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30
2010-08-01 09:10:47 +02:00
Peter Stuge 8772355bbd Remove srst_pulls_trst from LPC2148 target
srst_pulls_trst is only true on some (broken) LPC2148 boards, a fact
which is already documented in doc/openocd.texi, so it shouldn't be
set unconditionally in the target tcl.

This patch was needed to reflash when an Abort exception occured very
early after reset, before OpenOCD tried to halt the CPU.
2010-08-01 09:10:47 +02:00
Øyvind Harboe f4c1f08f16 lpc7168: make flash available upon reset init
set user mode to avoid ROM being mapped at address
0 rather than flash.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-30 22:36:00 +02:00
Spencer Oliver 8dbe367c53 cfg: add Amontec JTAGkey2p interface config (Issue #26)
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-07-19 17:31:38 +01:00
Spencer Oliver 4611f87f0a flash: add nuc910 nand driver
This adds a nand driver support for the nuc910 target.
Note that ECC is not currently supported by this driver, although
it is supported by the peripheral.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-07-19 12:22:18 +01:00
Spencer Oliver 8f5e84bf8d cfg: update rsc-w910 script
- Only enable the FMI (NAND) and DMA clocks.
 - Select NAND interface on the MFSEL.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-07-19 09:10:54 +01:00
David Brownell 2fdc1db304 lm3s811-ek uses generic stellaris target config
There's no point in an lm3s811-specific target file,
so remove it in favor of the generic "stellaris.cfg".

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-07-17 02:59:23 -04:00
Spencer Oliver 1619facb5e cfg: add Avalue RSC-W910 config
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-07-13 14:17:00 +01:00
Olaf Lüke 2986320cde at91sam3s* support
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-25 21:37:53 +02:00
Øyvind Harboe 4fa3cc7746 am3517 evm: use physical write to memory while target is running
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-22 12:49:56 +02:00
Øyvind Harboe fe1f7f63b6 board: add alpha am3517evm ti board config file
Signs of life: reset(kinda), halt, resume and memory
display/modify.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-22 08:22:01 +02:00
Thomas Koeller c9e2d13cf9 DM36x: pll & clock setup
Added a function 'pll_v03_setup' to set up PLLs and clock
dividers on DM365 and DM368.

Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-15 10:40:05 +02:00
michal smulski bf3410fcc7 arm1136 scripts
Here is a patch to fix a startup in C100 (arm1136). Basically make sure
that UART is configured before using it.

Michal

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-15 07:39:59 +02:00
Spencer Oliver 94dc7c0a93 cfg: add pic32 virtual banks
make use of the new virtual bank flash driver.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-05-26 11:10:15 +01:00
Freddie Chopin f1c1bed39a There are no variants of arm7tdmi target
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-05-24 09:21:40 +01:00
Freddie Chopin e2c9518eda All LPC2xxx chips are little endian and that cannot be changed - update config scripts
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-05-24 09:21:30 +01:00
Freddie Chopin 9c3b4cfc5d add correct CPUTAPID value for LPC2129
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-05-24 09:21:18 +01:00
Freddie Chopin 0e4f4bacdc Update "flash bank" helper comments for LPC2xxx chips
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-05-24 09:21:08 +01:00