update IXP42x target / XBA board config
This commit is contained in:
Michael Schwingen
Øyvind Harboe
parent
6839618062
commit
23bf724e04
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@ -0,0 +1,47 @@
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# board config file for AcTux3/XBA IXP42x board
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# Date: 2010-12-16
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# Author: Michael Schwingen <michael@schwingen.org>
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reset_config trst_and_srst separate
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adapter_nsrst_delay 100
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jtag_ntrst_delay 100
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source [find target/ixp42x.cfg]
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
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$_TARGETNAME configure -event reset-init { init_actux3 }
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proc init_actux3 { } {
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##########################################################################
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# setup expansion bus CS
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##########################################################################
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mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
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mww 0xc4000004 0x94d10013 ;#CS1
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mww 0xc4000008 0x95960003 ;#CS2
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mww 0xc400000c 0x00000000 ;#CS3
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mww 0xc4000010 0x80900003 ;#CS4
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mww 0xc4000014 0x9d520003 ;#CS5
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mww 0xc4000018 0x81860001 ;#CS6
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mww 0xc400001c 0x80900003 ;#CS7
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ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
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#mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
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ixp42x_set_bigendian
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flash probe 0
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}
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proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
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echo "writing bootloader: $FILE"
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flash write_image erase $FILE 0x50000000 bin
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}
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
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init
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reset init
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@ -1,6 +1,5 @@
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#xscale ixp42x CPU
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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@ -17,16 +16,92 @@ if { [info exists ENDIAN] } {
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0xffffffff
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set _CPUTAPID 0x19274013
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}
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set _CPUTAPID2 0x19275013
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set _CPUTAPID3 0x19277013
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set _CPUTAPID4 0x29274013
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set _CPUTAPID5 0x29275013
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set _CPUTAPID6 0x29277013
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#use combined on interfaces or targets that can?t set TRST/SRST separately
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reset_config srst_only srst_pulls_trst
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#jtag scan chain
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jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
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# register constants for IXP42x SDRAM controller
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global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
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global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
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set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000
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set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001
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global IXP42x_SDRAM_CL3
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global IXP42x_SDRAM_CL2
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set IXP42x_SDRAM_CL3 0x0008
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set IXP42x_SDRAM_CL2 0x0000
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global IXP42x_SDRAM_8MB_2Mx32_1BANK
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global IXP42x_SDRAM_16MB_2Mx32_2BANK
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global IXP42x_SDRAM_16MB_4Mx16_1BANK
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global IXP42x_SDRAM_32MB_4Mx16_2BANK
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global IXP42x_SDRAM_32MB_8Mx16_1BANK
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global IXP42x_SDRAM_64MB_8Mx16_2BANK
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global IXP42x_SDRAM_64MB_16Mx16_1BANK
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global IXP42x_SDRAM_128MB_16Mx16_2BANK
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global IXP42x_SDRAM_128MB_32Mx16_1BANK
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global IXP42x_SDRAM_256MB_32Mx16_2BANK
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set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030
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set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031
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set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032
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set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033
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set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010
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set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011
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set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012
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set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013
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set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014
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set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015
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# helper function to init SDRAM on IXP42x.
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# SDRAM_CFG: one of IXP42X_SDRAM_xxx
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# REFRESH: refresh counter reload value (integer)
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# CASLAT: 2 or 3
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proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
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switch $CASLAT {
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2 {
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set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
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set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
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}
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3 {
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set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
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set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
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}
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default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
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}
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echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
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mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
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mww 0xCC000004 0 ;# disable refresh
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mww 0xCC000008 3 ;# NOP
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sleep 100
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mww 0xCC000004 $REFRESH ;# set refresh counter
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mww 0xCC000008 2 ;# Precharge All Banks
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sleep 100
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3
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}
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proc ixp42x_set_bigendian { } {
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reg XSCALE_CTRL 0xF8
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}
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@ -1,88 +0,0 @@
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#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME xba_reva3
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# default to big endian
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set _ENDIAN big
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0xffffffff
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}
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reset_config trst_and_srst separate
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adapter_nsrst_delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
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$_TARGETNAME configure -event reset-init {
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#############################################################################
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# setup expansion bus CS, disable external wdt
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#############################################################################
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mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
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mww 0xc4000004 0x94d10013 ;#CS1
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mww 0xc4000008 0x95960003 ;#CS2
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mww 0xc400000c 0x00000000 ;#CS3
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mww 0xc4000010 0x80900003 ;#CS4
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mww 0xc4000014 0x9d520003 ;#CS5
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mww 0xc4000018 0x81860001 ;#CS6
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mww 0xc400001c 0x80900003 ;#CS7
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#############################################################################
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# init SDRAM controller: 16MB, one bank, CL3
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#############################################################################
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mww 0xCC000000 0x2A ;# SDRAM_CFG: 64MBit, CL3
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mww 0xCC000004 0 ;# disable refresh
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mww 0xCC000008 3 ;# NOP
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sleep 100
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mww 0xCC000004 2100 ;# set refresh counter
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mww 0xCC000008 2 ;# Precharge All Banks
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sleep 100
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 1 ;# Mode Select CL3
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#mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash
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#mirror at 0x00000000
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#big endian
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reg XSCALE_CTRL 0xF8
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#
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# detect flash
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#
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flash probe 0
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}
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$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
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init
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reset init
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# set big endian mode
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reg XSCALE_CTRL 0xF8
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