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Author SHA1 Message Date
Tim Newsome 4d264b3579 Put early DEBUG notice of XLEN back. 2017-06-19 08:46:02 -07:00
Tim Newsome 6082f35a55 Update debug_defines. Clarify debug output. 
Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
 2017-06-16 14:02:25 -07:00
Tim Newsome fd81f7fcac Fix comment. 2017-06-16 14:02:25 -07:00
Tim Newsome 851849a295 Tell the user about detected harts. 2017-06-16 14:02:25 -07:00
Tim Newsome 3abb347bd9 Tighten up debug output. 
Assuming the program allocating code works, we don't need its output.
Only output parts of the debug RAM that are actually doing something.
 2017-06-16 14:02:25 -07:00
Tim Newsome ac2da40f74 Fix indentation to match OpenOCD style. 
This change is just in the whitespace. There are no code changes.

See http://openocd.org/doc-release/doxygen/stylec.html
 2017-06-15 12:44:50 -07:00
Tim Newsome 363a0a2bf2 Merge pull request #64 from riscv/release-fixes 
Two fixes from the release branch
 2017-06-15 12:43:46 -07:00
Tim Newsome 50a223ef9a Fix print statements to work with 64-bit addresses 2017-06-15 12:24:37 -07:00
Palmer Dabbelt afc9eb6c47 Jump to the RTOS hartid after halting 
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting.  This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
 2017-06-15 12:16:33 -07:00
Palmer Dabbelt 099a3020d2 Clear abstract errors from register_read_direct 2017-06-15 12:16:24 -07:00
Tim Newsome 64af052911 Fix the build. 
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
 2017-06-13 12:33:01 -07:00
Tim Newsome 6be600318c Fix dmi_read() indentation; remove \n in LOG_ERROR 2017-06-08 12:31:08 -07:00
Megan Wachs c3b344d1c0 riscv: Move the initialization of the field inside the structure for consistency 2017-06-07 21:06:33 -07:00
Megan Wachs 459b39ec67 riscv: v13 -- dmi_write must still check for the OP result 2017-06-07 21:06:33 -07:00
Tim Newsome 11008baee3 %p already includes 0x (on gcc) 2017-06-06 11:51:15 -07:00
Palmer Dabbelt ab77c5d792 Invalidate the register cache when rtos_hartid==-1 
This means I don't know what hart to look at, so I might as well
invalidate the register cache.  Without this, you might get stale
registers the first time you ask for them.
 2017-05-25 13:14:31 -07:00
Palmer Dabbelt faa6123e36 Invalidate the register cache on step, resume, reset 
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode.  With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
 2017-05-25 13:14:31 -07:00
Megan Wachs e12f5575ef riscv-v11: Don't perform unexpected operation in cache_write 2017-05-22 22:02:01 -07:00
Palmer Dabbelt c431c0eb25 Check for abstractcs.busy, not just CMDERR_BUSY 
This fixes a race condition when reading/writing memory.
 2017-05-15 17:40:28 -07:00
Palmer Dabbelt a8cf04b839 Go back to 32-word read/write buffers 
The larger buffers are really slow on Spike.
 2017-05-15 16:57:25 -07:00
Palmer Dabbelt e31761df64 Don't re-read registers after they're written 
This was just a sanity check.
 2017-05-15 16:57:08 -07:00
Palmer Dabbelt 9d308db2bc Print out the actual CSR that's read 2017-05-15 16:56:50 -07:00
Palmer Dabbelt 8252b9d36c Build fixes 2017-05-15 13:39:58 -07:00
Megan Wachs af6e04d5c0 riscv: Remove some compile warnings 2017-05-15 13:36:05 -07:00
Palmer Dabbelt bcf2a16b0d Shim back in some old interfaces for now 2017-05-11 10:41:13 -07:00
Palmer Dabbelt 563f6acc3c Allow all harts to be reset 2017-05-09 13:33:20 -07:00
Megan Wachs fa8d7adf33 Avoid accessing null target->reg_cache 
GDB might request registers even if target was not successfully initialized.
 2017-05-05 11:05:28 -07:00
Megan Wachs 95a2eb157a riscv-013: more consistent parens 2017-05-01 09:42:11 -07:00
Megan Wachs 458bb20699 riscv-013: Correct sign extension of address on read_memory for lower bits as well 2017-05-01 09:39:59 -07:00
Megan Wachs 8462750357 riscv-013: Correct sign extension of address on read_memory 2017-05-01 09:37:48 -07:00
Megan Wachs ad1cf13ef4 Correct debugging print in read_memory 2017-05-01 08:35:10 -07:00
Palmer Dabbelt 16de5044d4 Fix an assertion when reading from 0 2017-05-01 08:33:01 -07:00
Palmer Dabbelt ba3a56937b Correct previous hart caching logic 2017-05-01 08:32:43 -07:00
Palmer Dabbelt 1ec607c726 Clean up unused read_memory code 2017-04-27 12:56:01 -07:00
Palmer Dabbelt 17d04aded3 Keep calling the old poll on v0.11 targets 
This is another thing that should be fixed correctly.  Essentially this
just uses the old codepath, which works for v0.11.
 2017-04-26 15:16:39 -07:00
Palmer Dabbelt 9d4df3420c Initialize all registers in examine 
I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt.  This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
 2017-04-26 15:09:24 -07:00
Megan Wachs da66be0161 riscv: Fix some blocking compile warnings 2017-04-26 10:23:53 -07:00
Palmer Dabbelt 8dea2908b7 Add 64-bit and multihart support 
This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest draft version of the RISC-V debug spec, as of
   April 26th.  This version fixes a number of spec bugs and should be
   close to the final debug spec.
 2017-04-26 09:10:49 -07:00
Megan Wachs 3dc066382b Properly consider 'reset halt' and do halt or resume as needed 2017-04-10 12:03:15 -07:00
Megan Wachs b04c6cb3ed riscv: Implement the assert/deassert reset functions for v13 2017-04-10 12:03:15 -07:00
Megan Wachs 14e26040b8 riscv: move value read to after autoexec is cleared. 2017-04-04 16:33:17 -07:00
Megan Wachs 9c1f6ea28b riscv: Correct the autoexec in read_mem 2017-04-04 16:22:55 -07:00
Megan Wachs eb90a5e05e riscv: Use write-1-to-clear for CMDERR, not write 0 to clear. 2017-03-30 14:27:28 -07:00
Palmer Dabbelt 03fa9d22c4 Don't set abstractauto at the start 2017-03-23 14:50:40 -07:00
Megan Wachs c61b3efe9a riscv: Retry failed memory reads 2017-03-22 17:51:46 -07:00
Megan Wachs 98420e377a riscv: add missing variable declaration. 2017-03-21 23:47:21 -07:00
Palmer Dabbelt 09da0c812f Clear autoexec correctly 2017-03-21 17:20:11 -07:00
Palmer Dabbelt 6033850415 Wrong autoexec 2017-03-21 17:20:11 -07:00
Palmer Dabbelt 0c790d385d Builds 2017-03-21 17:20:11 -07:00
Megan Wachs a70e628620 riscv-v13: wait for idle in read_memory 
read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.
 2017-03-15 17:23:21 -07:00
Tim Newsome bb39d3b17e Remove more cruft. 
Change-Id: I24d545cc259927301851fad446f812e95fd1c557
 2017-02-27 20:27:07 -08:00
Megan Wachs 7f13e90505 riscv: Ensure that hart is halted before attempting to examine it. 2017-02-27 18:53:50 -08:00
Tim Newsome b4d38d0997 Remove cruft. 
Change-Id: I3a370aa3a478ab84c9b2afff7b3f581bd7dc5e06
 2017-02-25 10:40:56 -08:00
Tim Newsome 6f1a498ab9 Use DCSR constants from the debug spec. 
Replace the constants with the ones from the ISA spec, since those are
not updated as often.

Also delete a bunch of old code.

Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
 2017-02-25 10:34:46 -08:00
Tim Newsome 8f6ddc92e8 Update bits to latest spec. 
Change-Id: Ib09e1da81c6c0e7c9c6b69e9fe31eda20e3cd6e0
 2017-02-25 10:17:27 -08:00
Tim Newsome 3bd661b679 Speed things up by ignoring return values. 
The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.

That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.

Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
 2017-02-22 16:04:36 -08:00
Tim Newsome f9168b09d0 Optimize memory write code, used in download. 
To spike now we download at 5KB/s. But in real hardware performance
should be pretty OK now.

Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
 2017-02-21 20:31:50 -08:00
Tim Newsome 4e8cf4aeb5 Better error checking in memory access. 
Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
 2017-02-20 17:53:18 -08:00
Tim Newsome aba0c0973d Properly restore s0 and s1 on resume. 
Now 33/39 of the gdbserver tests pass!

Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
 2017-02-20 15:47:31 -08:00
Tim Newsome 3173314f28 Fix access FPU registers again. 
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.

Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
 2017-02-17 19:03:32 -08:00
Tim Newsome 071f9a2916 Fix use of REG vs CSR constants. 
23 gdbserver.py tests pass now.

Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b
 2017-02-17 12:35:43 -08:00
Tim Newsome b363d1a37e Bunch of register access refactoring. 
Got rid of the last reference to the old debug RAM code! (Mostly?)
SimpleF18Test passes now.

Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be
 2017-02-17 11:53:37 -08:00
Tim Newsome 88f14f4d5e Check busy before triggering another command. 
This version was able to download code, and run to a breakpoint.

Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
 2017-02-16 14:21:17 -08:00
Tim Newsome ef3875a320 Check for errors after read/write. 
The code doesn't do anything intelligent if errors are found.
But MemTestBlock now also passes. I'm not quite sure why.

Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
 2017-02-15 20:41:39 -08:00
Tim Newsome 035b4dd17a Fix double read, which might have side effects. 
Now passing MemTest{8,16,32,64}

Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
 2017-02-15 19:05:51 -08:00
Tim Newsome 713c001242 Make MemTest32 pass. 
Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513
 2017-02-15 17:10:53 -08:00
Tim Newsome 79e840aaa7 Some memory access works. 
MemTest16 passes, but MemTest32 fails.

Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65
 2017-02-15 15:44:36 -08:00
Tim Newsome ceb8dc048d Make general CSR reads work. 
Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd
 2017-02-14 12:55:03 -08:00
Tim Newsome ae4fda2719 Make it all the way through examine(). 
This includes reading GPRs (although I haven't confirmed the values) and
doing some CSR reading/writing to disable triggers that may be left over
from a previous setting.

Change-Id: I2c627bd002d601e302a40f838087541897c025fd
 2017-02-14 11:43:58 -08:00
Tim Newsome 00925574d5 More dbus->dmi. 
Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb
 2017-02-14 09:38:09 -08:00
Tim Newsome 24033b53d8 Read misa during examine(), using program buffer. 
Change-Id: Icad5324d216b61207cb5f6024b2deab065658640
 2017-02-13 21:29:02 -08:00
Tim Newsome 0fa8162a8c dbus -> dmi 
Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839
 2017-02-13 11:13:14 -08:00
Tim Newsome e2a5e02d1c Discover XLEN using abstract reg reads. 
Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b
 2017-02-13 09:54:05 -08:00
Tim Newsome e6221e75c9 Attempt to discover XLEN with abstract reg reads 
Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
 2017-02-10 19:08:44 -08:00
Tim Newsome 5e3d9803ab Halt target in riscv_examine(). 
Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
 2017-02-10 11:31:14 -08:00
Tim Newsome 075c0e80d1 Add debug_defines.h. 
Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893
 2017-02-09 09:57:54 -08:00
Tim Newsome 2ad366e658 Detect and smoketest data and ibuf registers. 
Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207
 2017-02-08 20:40:37 -08:00
Tim Newsome 8cac7d0cee Correctly parse dmcontrol. 
Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4
 2017-02-08 19:47:34 -08:00
Tim Newsome 8af4a9a053 Update DMI bus width for 0.13. 
Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
 2017-02-07 11:28:50 -08:00
Tim Newsome ecc5b6ecad Add missing header file. 
Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df
 2017-02-05 21:32:44 -08:00
Tim Newsome 6f78eb1ec1 Add the first difference for 0.13 targets. 
Just to confirm the 0.13 code takes a different path.

Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36
 2017-02-05 18:21:34 -08:00
Tim Newsome 8d195afd2d Use the csrNNN name instead of "mstatus". 
Fixes flashing code.

Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
 2017-02-05 18:19:00 -08:00
Tim Newsome d055f86552 Most gdbserver tests pass now. 
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
 2017-02-05 18:09:19 -08:00
Megan Wachs 5d82a395f1 riscv: disable interrupts for all priviledge levels 2017-01-25 21:51:02 -08:00
Megan Wachs d5892f0ee5 riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms. 2017-01-25 15:23:10 -08:00
Megan Wachs 5766efe0c3 riscv: Globally disable interrupts when running algorithms. 2017-01-25 11:35:57 -08:00
Megan Wachs 4a0d3fb035 riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just get a segfault when attempting to perform these actions. 2016-12-07 15:09:35 -08:00
Tim Newsome c1da323144 Fix issue #6: build failure on gcc 6 
Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078
 2016-12-01 19:15:55 -08:00
Tim Newsome 7dd48acdc0 Cope better if the target unexpectedly resets. 
Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9
 2016-11-25 09:46:55 -08:00
Tim Newsome 8ee0647365 Flash at 8KB/s, using 10,000 byte working area. 
If the working area is large enough, every fespi_write() results in just
a single algorithm execution.

Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
 2016-11-18 10:58:26 -08:00
Tim Newsome 18eedf996c Use algorithm to speed up fespi flash programming. 
It's still really slow, at 854b/s, but it seems to work and it's a lot
of new code.

Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
 2016-11-16 17:54:55 -08:00
Tim Newsome e51b0360f5 Make fpu regs work even if mstatus.fs is 0. 
Change-Id: I2c283f2de226518ab9a4e0476edada51825b2993
 2016-11-01 12:58:37 -07:00
Tim Newsome e7a745ed3b Fix bug with slow targets. 
Halting didn't work right in slow targets, because some code assumed the
register cache is valid before it was guaranteed to be.

Also made dbus_busy_delay and interrupt_high_delay grow faster, so that
on slow targets it takes less time to learn the correct values.

Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42
 2016-10-27 13:00:26 -07:00
Tim Newsome e6e2070692 Add some comments. 
Change-Id: Icd7d5eb370c6c893ec4717c92249f35fb100370a
 2016-10-24 14:21:34 -07:00
Tim Newsome 3eb6cf0fc0 Make CLI step and resume work. 
Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
 2016-10-20 14:49:23 -07:00
Tim Newsome 9b0be80d1e Use reg_cache structure, to make reg command work. 
Change-Id: I9f1d1f2eab66822c3c47284aa91b52cc34998381
 2016-10-20 10:42:28 -07:00
Tim Newsome 4eba841bfe Print when we're ready for gdb to connect. 
This should help gdbserver.py to connect reliably to really slow targets
(ie. simulators).

Change-Id: I8e9adbaf2ebde11b44e15582f036622a2d00c1f9
 2016-10-14 12:40:52 -07:00
Tim Newsome 3f6c2a9f78 Be quiet when the target is just running normally. 
Change-Id: I7861f16ba6b1b5c1851787ce5d78c02aff0568f6
 2016-10-13 10:51:53 -07:00
Tim Newsome cb93bb9035 Use an easily changed constant for timeout. 
Change-Id: I7aace463b0bd9916580e950d60b2940879b27b2a
 2016-10-11 16:26:19 -07:00
Tim Newsome 4882de94cc Display pc to the user in 'monitor reset init'. 
Change-Id: Ifb8df31954dfc5a3badef4f0a29eb510a97310a2
 2016-10-10 08:22:51 -07:00
Tim Newsome a08cef7633 Change invalid access from error to user message. 
It's not a failure in the debugger or even a real problem if a user asks
to access memory that's not accessible.

Change-Id: I30b8424d5265d1996fe4826012ed160a83f0bc6c
 2016-10-03 08:15:04 -07:00
Tim Newsome e273e23f41 Fix off-by-one error in assert. 
Also only do work for debug RAM that actually exists on the target
(exposing the off-by-one error on 32-bit targets).

Change-Id: I37e0005b6a70e949286f1d6494716f3abea03c12
 2016-09-29 10:40:50 -07:00
Tim Newsome 4dbc9962d3 Clear dmode triggers when we first halt the target 
This helps repeated runs of the testsuite pass, and is probably a good
idea in general.

Change-Id: I89ed167968f8b8817c66f1718f374d0c502780c7
 2016-09-29 10:23:46 -07:00
Tim Newsome 78fe0b56db Deal with dbus being busy in all cases. 
Change-Id: Ifede6e05c3c4538f22a52cd0e9833cf3a9983d04
 2016-09-29 08:28:31 -07:00
Tim Newsome b04d5e8821 Read idle, and test all debug RAM. 
Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.

In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.

Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
 2016-09-27 13:06:32 -07:00
Tim Newsome c67850b63d Only write to existing dram. Clear dbus error. 
Old code would write 64 bytes of DRAM if the dbus was busy in
cache_write().

New code clears the dbus error condition when the bus is busy. (This
part is untested.)

Change-Id: Ia396fe819fa1828bb75726d85513b113cc9e13f0
 2016-09-27 08:45:51 -07:00
Tim Newsome 54c65a9a4b Improve low-level logging. 
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters up the
log/screen and is not generally helpful.
 2016-09-23 14:16:24 -07:00
Tim Newsome 08228e6f53 Make more code use the scans "class". 
Helps with consistency, and this is a rare commit that net deletes
lines.
 2016-09-23 14:16:24 -07:00
Tim Newsome cf1dc0b6cb Implement hardware triggers that match spec. 
It's basically working, but the following corner cases are failing:
    TriggerDmode
    TriggerLoadAddressInstant
    TriggerStoreAddressInstant
 2016-09-23 14:16:24 -07:00
Tim Newsome 526bbc5284 Optimize read a bit. 
Remove some unnecessary scans.
 2016-09-23 14:16:24 -07:00
Tim Newsome c68b13ed67 Properly mark the cache as clean after its written 
This reduces the number of scans, but I doubt it noticeably improves
performance.
 2016-09-23 14:16:24 -07:00
Tim Newsome 243233c8b8 Convert some more code for 64-bit. 2016-09-23 14:16:24 -07:00
Tim Newsome b04f89076a Properly write 64-bit PCs. 2016-09-23 14:16:24 -07:00
Tim Newsome e3e745abb9 WIP for 64-bit support. 
GPR register writes/reads seem to work.
 2016-09-23 14:16:24 -07:00
Tim Newsome 2f1b6b5803 Stop using conditional writes. 
It doesn't help, and makes the spec more complex. Now that I've proven
OpenOCD doesn't need it, I'll remove it from the spec.
 2016-09-23 14:16:24 -07:00
Tim Newsome 5dbad6b0c9 Check for business in block reads. 2016-09-23 14:16:24 -07:00
Tim Newsome f8b0f4bf29 Check for exceptions in reads and writes. 2016-09-23 14:16:23 -07:00
Tim Newsome f5ae4d864c Add support for virtual priv register. 
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
 2016-09-23 14:16:23 -07:00
Tim Newsome 5de81da8f4 Remove commented out code. 
Also added back the initial check that confirms debug RAM is written
correctly.
 2016-09-23 14:16:23 -07:00
Tim Newsome a916d204b9 Optimize memory read. 
Saves 8s on the full test suite.
 2016-09-23 14:16:23 -07:00
Tim Newsome 32e7a962c3 Write fence.i before dret. 
Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
 2016-09-23 14:16:23 -07:00
Tim Newsome 4ced71b1f1 Log more. 2016-09-23 14:16:23 -07:00
Tim Newsome 20e2bfe3db Quickly read all GPRs on halt. 
gdb will ask for them anyway, and one by one is slow.
StepTest went from 9.7s to 5.3s.
 2016-09-23 14:16:23 -07:00
Tim Newsome 6fac5a41f8 Remove some hwbp debug code. 2016-09-23 14:16:23 -07:00
Tim Newsome 7dcc0681d4 Speed up some other operations. 2016-09-23 14:16:23 -07:00
Tim Newsome 1fdcfa7082 Speed up register read. 
Don't scan an extra sequence just to read the return value.
 2016-09-23 14:16:23 -07:00
Tim Newsome 27b94d36d0 Fix 32-bit build. 2016-09-23 14:16:23 -07:00
Tim Newsome 668070cc45 Faster download. 
16K testcase:
Transfer rate: 53 KB/sec, 2222 bytes/write.
 2016-09-23 14:16:23 -07:00
Tim Newsome 9aab0aa068 Minor cleanup. 2016-09-23 14:16:23 -07:00
Tim Newsome 06f6b5020c Use optimized cache/program write scheme for most 
operations.
 2016-09-23 14:16:23 -07:00
Tim Newsome a1875fbecf Working on optimized program running. 
Makes a big difference on the XLEN code (29ms to 8ms). Now to use it in
more places.
 2016-09-23 14:16:23 -07:00
Tim Newsome 9b9653ab7d Use hardware single step. 2016-09-23 14:16:23 -07:00
Tim Newsome eac8933b89 WIP on performance improvement. 
Also implement empty arch_state to prevent occasional startup crash.
 2016-09-23 14:16:23 -07:00
Tim Newsome 2d02e77bed Make this compile for 32-bit targets. 2016-09-23 14:16:23 -07:00
Tim Newsome aaa8ce10b8 Correctly figure out the number of extant hwbps. 2016-09-23 14:16:23 -07:00
Tim Newsome c471cfb63b Simple execute hardware breakpoint works. 2016-09-23 14:16:23 -07:00
Tim Newsome cb57aa55fa Deal with exceptions on register read. 
Cache dpc, so we can restore it when it's clobbered by an exception.
 2016-09-23 14:16:23 -07:00
Tim Newsome b81a846be5 Cache dcsr, since we're reading it anyway. 2016-09-23 14:16:23 -07:00
Tim Newsome c8430bb8f4 DebugTest.test_interrupt passes now. 2016-09-23 14:16:23 -07:00
Tim Newsome e10d407623 Speed up memory read a little. 2016-09-23 14:16:23 -07:00
Tim Newsome 4b19b7305f Save/restore T0 around block writes. 2016-09-23 14:16:23 -07:00
Tim Newsome 90f458e63f Reading/writing s1 now works. 2016-09-23 14:16:23 -07:00
Tim Newsome 0881092d9b Can successfully run to a swbp. 2016-09-23 14:16:23 -07:00
Tim Newsome c364bd0ab5 We can run to a software breakpoint, but 
gdb doesn't notice we're halted once we hit it, even though riscv_poll()
is setting the target state to halted.
 2016-09-23 14:16:23 -07:00
Tim Newsome 04cfc35147 Use the dram cache to save some scans. 2016-09-23 14:16:23 -07:00
Tim Newsome dce4a992a3 Single memory reads/writes work. 2016-09-23 14:16:23 -07:00
Tim Newsome 1b349df638 WIP hackery. 
Main thing I added is code to output "verilog" for every JTAG op we do,
so we can run the same thing in simulation.
 2016-09-23 14:16:23 -07:00
Tim Newsome f40862d87c Go through run-test/idle once per dbus access. 2016-09-23 14:16:23 -07:00
Tim Newsome 9f22176618 Reading registers appears to work. 2016-09-23 14:16:23 -07:00
Tim Newsome 84944ded87 Fix up some register stuff. 
Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
 2016-09-23 14:16:23 -07:00
Tim Newsome f634702aaf Successfully determine xlen. 
There's a nop in there for no reason, though.
 2016-09-23 14:16:23 -07:00
Tim Newsome db06dd45a0 Improve error checking. 2016-09-23 14:16:23 -07:00
Tim Newsome 041e0ccf9e Selecting dbus is sometimes necessary. 2016-09-23 14:16:22 -07:00
Tim Newsome 25e8b66b08 WIP registers. 2016-09-23 14:16:22 -07:00
Tim Newsome 3b60c3aa42 Fix bug when waiting for debugint to clear. 2016-09-23 14:16:22 -07:00
Tim Newsome 67009979ae Clearer debug logging. 2016-09-23 14:16:22 -07:00
Tim Newsome 3b3beb04ef WIP on registers. 2016-09-23 14:16:22 -07:00
Tim Newsome 482497c51a Blind implementation of write_memory. 2016-09-23 14:16:22 -07:00
Tim Newsome 50ca8ac373 Blind implementation of read_memory. 2016-09-23 14:16:22 -07:00
Tim Newsome 76fe7db0db In theory assert_reset/deassert_reset work. 2016-09-23 14:16:22 -07:00
Tim Newsome ea6836c5f6 WIP, blind coding. 2016-09-23 14:16:22 -07:00
Tim Newsome 413ab49dfd Blind coding new dbus behavior. 2016-09-23 14:16:22 -07:00
Tim Newsome feff2dd9e7 Always leave the TAP in Run-Test/Idle. 2016-09-23 14:16:22 -07:00
Tim Newsome 98f2fa897f Halt should work now. 2016-09-23 14:16:22 -07:00