Instead of making people type this in all the time, just default to
"SEGGER RTT" so more things work out of the box.
Change-Id: I147142cf0a755e635d3f66e047be2eb5049cf511
Signed-off-by: Karl Palsson <karl.palsson@marel.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8354
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Open output file in binary mode to disable EOL
conversion on Windows (and sometimes cygwin depending
on installation settings and path).
Change-Id: I38276dd1af011ce5781b0264b7cbb08c32a1a2ad
Signed-off-by: Richard Allen <rsaxvc@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8278
Reviewed-by: Karl Palsson <karlp@tweak.au>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This is useful for setting a reset catch on a CPU that is being
brought out of reset.
Change-Id: Id8fe9bc3f75fd170f207f470a9f3b0faba7f24c1
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8422
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reduce the amount of boilerplate by moving cti_regs into its only
user, making it a local variable and removing the now-redundant
p_val pointer.
Change-Id: I778cc1e960532fae1ac1a952c6ff19c54e578a5f
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8421
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Some targets start up with the sticky overrun bit set. On such targets
we need to clear it in order to avoid subsequent incorrect reads.
Change-Id: I3e939a9e092de6fcea9494d3179a3386aa1701d2
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8420
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
While at it, fix some small coding style issues.
Change-Id: Ifb8e78b55d29a06d69a3ce71d12d0040777aef13
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8423
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The function str_to_buf() can be simplified by writing directly
the intermediate results in the output buffer.
Such simplification improves the readability and also makes
scan-build happy, as it does not trigger anymore the warning:
src/helper/binarybuffer.c:328:8: warning: Use of memory
allocated with size zero [unix.Malloc]
if ((b256_buf[(buf_len / 8)] & mask) != 0x0) {
Change-Id: I1cef9a1ec5ff0e5841ba582610f273e89e7a81da
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8396
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Tested-by: jenkins
The name 'buf_len' is misleading, as it usually refers to the byte
length of a buffer. Here we use it for the length in bits.
Rename it as 'buf_bitsize'.
While there, fix checkpatch error by changing the index type to
'unsigned int'.
Change-Id: I78855ed79a346d996d9c0100d94d14c64a36b228
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8395
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
With 'radix' always zero and '_detected_radix' always NULL, drop
the two parameters and simplify str_to_buf().
While there:
- drop some redundant assert(),
- drop the re-check for the base prefix,
- simplify str_strip_number_prefix_if_present() and rename it, as
the prefix MUST be present,
- fix a minor typo,
- update the doxygen description of str_to_buf().
Change-Id: I1abdc8ec0587b23881953d3094101c04d5bb1c58
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8394
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Commit 53b94fad58 ("binarybuffer: Fix str_to_buf() parsing
function") introduces the helper command_parse_str_to_buf() to
parse as number a string on TCL command-line.
The parameter 'radix' can specify the base (decimal, octal,
hexadecimal, or auto-detected).
TCL is supposed to use decimal numbers by default, while octal and
hexadecimal numbers must be prefixed respectively with '0' and
'0x' (or '0X').
This would require the helper to always run auto-detection of the
base, thus always set the 'radix' parameter to zero. This makes
the parameter useless.
Keeping the 'radix' parameter can open the door to future abuse of
TCL syntax, E.g. a command can require an octal value without the
mandatory TCL '0' prefix; the octal value cannot be the result of
TCL expression.
To prevent any future abuse of the 'radix' parameter, drop it.
Change-Id: I88855bd83b4e08e8fdcf86a2fa5ef3269dd4ad57
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8393
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
The telnet 'exit' command is only available in the execution phase of
OpenOCD. Thus, a telnet session cannot be closed via 'exit' if OpenOCD
is started with 'noinit'. Make the 'exit' command always available.
Change-Id: I14447ecde63e579f1c523d606f048ad29cc84a35
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8379
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Do not echo the selected transport to avoid stray and confusing
messages in the output of OpenOCD. For example, the "swd" line here:
Open On-Chip Debugger 0.12.0+dev-00559-ge02f6c1b9-dirty
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
swd
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
While at it, fix some small documentation style issues.
Change-Id: Ie85426c441289bbaa35615dbb7b53f0b5c46cfc0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8217
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The 'orig_instr' information of software breakpoints is incorrect
because buf_to_hex_str() expects the length of the buffer to be
converted in bits and not bytes.
Change-Id: I9a9ed383a8c25200d461b899749d5259ee4c6e3d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8218
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
While at it, apply some coding style fixes.
Change-Id: I77a6917a045af733ebe9211ca338952dbd49c89b
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8416
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be addresses
in following patches.
While at it, apply coding style fixes if these are not too extensive.
Change-Id: I364467b88f193f8387623a19e6994ef77899d117
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8414
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be addresses
in following patches.
While at it, apply coding style fixes if these are not too extensive.
Change-Id: Idcbbbbbea2705512201eb326c3e6cef110dbc674
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8413
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be addresses
in following patches.
While at it, apply coding style fixes if these are not too extensive.
Change-Id: Ie048b3d472f546fecb6733f17f9d0f17fda40187
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8404
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be modified
in following patches.
Change-Id: I83921d70e017095d63547e0bc9fe61779191d9d0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8403
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The jimtcl project supports pkg-config, use it for a simpler
configuration of compiler and linker flags and to enforce the minimum
required package version.
Since the jimtcl pkg-config file is not available on all systems, use
AC_CHECK_HEADER() as fallback.
Change-Id: I6fdcc818a8fdd205a126b0a46356434dbe890226
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8383
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Remove the hyphen from "pre-verify" in usage text.
Add preverify to the help text and procedure comment
Change-Id: I6d96e78ca84d99929300d461e435f5b4ce07b5db
Signed-off-by: Grant Ramsay <grant.ramsay@hotmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8376
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Scan-build is unable to detect that 'target->dbg_msg_enabled' does
not change across the function cortex_m_fast_read_all_regs().
It incorrectly assumes that it can be false at the first check (so
'dcrdr' get not assigned) and it is true later on (when 'dcrdr'
get used).
This triggers a false positive:
src/target/cortex_m.c:338:12: warning:
3rd function call argument is an uninitialized value
[core.CallAndMessage]
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
Use a local variable for 'target->dbg_msg_enabled' so scan-build
can track it as not modified.
While there, change the type of 'target->dbg_msg_enabled' to
boolean as there is no reason to use uint32_t.
Change-Id: Icaf1a1b2dea8bc55108182ea440708ab76396cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32U53/U54x devices are similar to U57/U58x devices
with 2 flash banks up to 256 KB each
Change-Id: I774ef0df4dddac5f06bbfc2e6c3fc2e628d2249e
Signed-off-by: FBOSTM <fedi.bouzazi@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7515
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32U59/U5Ax devices are similar to U57/U58x devices
with 2 flash banks up to 2 MB each
while at there update STM32U57x/U58x revisions
Change-Id: I7e5c1700acf8c9fda34f660c9274bfd8bcb1381b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6875
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
As defined in `target/target.h`, `coreid` is the index of the target on
the TAP, so, if an SMP group includes targets from multiple TAPs, it can
not be used as the base for `threadid`.
Change-Id: Ied7cfa42197aaf4908ef6628c6436f28d4856ebe
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7957
Tested-by: jenkins
Reviewed-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use a command group 'tcl' with subcommands instead of individual
commands with 'tcl_' prefix.
The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I1efd8a0e2c1403833f8cb656510a54d5ab0b2740
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8344
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Use a command group 'gdb' with subcommands instead of individual
commands with 'gdb_' prefix.
The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I037dc58554e589d5710cf46924e0a00f863aa300
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8336
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added FT4232HA varianet of FTDI's FT4232H which has a different bcd.
Also added default PID/VID for the FT4243HA to contrib/60-openocd.rules.
And added default PID/VIDs for FTDI's HP ICs to contrib/60-openocd.rules
as this wasn't done previously.
BugLink: https://sourceforge.net/p/openocd/tickets/410/
Change-Id: Ia84b566aa004332d3f7815a3d22ac37eee4f522a
Signed-off-by: Jonathan Forrest <jonyscathe@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8225
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The function str_to_buf() was too benevolent and did
not perform sufficient error checking on the input
string being parsed. Especially:
- Invalid numbers were silently ignored.
- Out-of-range numbers were silently truncated.
The following commands that use str_to_buf()
were affected:
- reg (when writing a register value)
- set_reg
- jtag drscan
This pull request fixes that by:
- Rewriting str_to_buf() to add the missing checks.
- Adding function command_parse_str_to_buf() which can
be used in command handlers. It parses the input
numbers and provides user-readable error messages
in case of parsing errors.
Examples:
jtag drscan 10 huh10
- Old behavior: The string "huh10" is silently
converted to 10 and the command is then executed.
No warning error or warning is shown to the user.
- New behavior: Error message is shown:
"'huh10' is not a valid number"
reg pc 0x123456789
Assuming the "pc" is 32 bits wide:
- Old behavior: The register value is silently
truncated to 0x23456789 and the command is performed.
- New behavior: Error message is shown to the user:
"Number 0x123456789 exceeds 32 bits"
Change-Id: I079e19cd153aec853a3c2eb66953024b8542d0f4
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8315
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The driver code works reliably, no need to use assert() everywhere.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Idb1942bfd31d370a74610b8a8836bc2e64370557
Reviewed-on: https://review.openocd.org/c/openocd/+/8324
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
nrf5_auto_probe() always re-probed chip hardware to
get flash geometry.
Introduce nrf5_probe_chip() and move chip related probing to it.
Save all flash parameters needed for bank setup to struct nrf5_info.
Introduce nrf5_setup_bank() and move bank setup code to it.
Call both chip probe and bank setup unconditionally from nrf5_probe():
in case of manual issuing 'flash probe' command, we should refresh actual
values from the device.
Call chip probe and bank setup only if not done before from
nrf5_auto_probe().
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ib090a97fd7a41579b3d4f6e6634a5fdf93836c83
Reviewed-on: https://review.openocd.org/c/openocd/+/8322
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ARM documentation for Cortex-M reports the field 'implementer' in
the register CPUID.
OpenOCD used the miss-spelled 'implementor'. Fix it!
Change-Id: I854d223971ae7a49346e1f7491c2c0415f5e2c1d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8318
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Add Cortex-M52 to the list of known Cortex-M implementations to
allow detection of the core.
Values checked against the ARM document "Arm China Cortex®-M52
Processor Technical Reference Manual" 102776_0002_06_en.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: Id0bde8a0476f76799b7274835db9690f975e2dd6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8317
Tested-by: jenkins
The detection of Cortex-M STAR-MC1 was introduced with [1], at a
time when OpenOCD was only checking the field PartNo of the CPUID
register.
Later-on [2], OpenOCD extended the check to the field implementer
of CPUID register. The value for ARM (0x41) implementer was used
to all the Cortex-M, but no feedback for STAR-MC1 was available. A
comment reporting the possible mismatch was added.
As reported on OpenOCD mailing-list, the technical reference manual
for STAR-MC1 is now available [3] and it reports the implementer
as ARM China (0x63) [3].
Fix the STAR-MC1 implementer accordingly.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: I8ed1064a847b73065528ee7032be967b5c58b431
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Link: [1] 7dc4be3157 ("target/arm: Add support with identify STAR-MC1")
Fixes: [2] 05ee889155 ("target/cortex_m: check core implementor field")
Link: [3] https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160
Reviewed-on: https://review.openocd.org/c/openocd/+/8316
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use a command group 'hla' with subcommands instead of individual
commands with 'hla_' prefix.
The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I612e3cc080d308735932aea0f11001428eadc570
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8335
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add space around math operators.
Change-Id: I50fce3da283a78ba02bf70b6a752f7bf778d79f5
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7585
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The flag '-coreid' is used by the command 'target create' to
specify the debug controller of the target, either in case of a
single debug controller for multiple CPU (e.g. RISC-V harts) or
in case of multiple CPU on a DAP access port (e.g. Cortex-A SMP
cluster).
It is also currently used to specify the CPU ID in a SMP cluster,
but this is going to be reworked.
This flag has no effects on Cortex-M; ARM specifies that only one
CPU Cortex-M can occupy the DAP access port by using hardcoded
addresses.
The flash driver 'psoc6' uses the flag '-coreid' to detect if the
current target is the Cortex-M0 on AP#1 or the Cortex-M4 on AP#2
in the SoC.
There are other ways to run such detection, without using such
unrelated '-coreid' flag, e.g. using the AP number or the arch
type of the target.
Use the arch type to detect Cortex-M0 (ARM_ARCH_V6M) vs Cortex-M4
(ARM_ARCH_V7M).
Drop the flags '-coreid' from the psoc6 configuration file.
Change-Id: I0b9601c160dd4f2421a03ce6e3e7c55c6212f714
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8128
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
When an asynchronous exception occurs at the same time
as a breakpoint event (either hardware breakpoint or software breakpoint),
it is possible for the processor to halt at the beginning of the
exception handler instead of the instruction address pointed
by the breakpoint.
During debug entry in exception handler state and with BKPT bit set
as the only break reason in DFSR, check if there is a breakpoint, which
have triggered the debug halt. If there is no such breakpoint,
resume execution. The processor services the interrupt and
halts again at the correct breakpoint address.
The workaround is not needed during target algo run (debug_execution)
because interrupts are disabled in PRIMASK register.
Also after single step the workaround resume never takes place:
the situation is treated as error.
Link: https://developer.arm.com/documentation/SDEN1068427/latest/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I8b23f39cedd7dccabe7e7066d616fb972b69f769
Reviewed-on: https://review.openocd.org/c/openocd/+/8332
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Liviu Ionescu
Most of the work is already done by [1].
Remove few more '_s' suffix and also fix some comment referring to
the old name of the struct.
Link: https://review.openocd.org/c/openocd/+/8340
Change-Id: Ifddc401c3b05e62ece3aa7926af1e78f0c4a671e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8341
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The output "gdb port disabled" is confusing without reference to the
target. Use LOG_TARGET_INFO() to output the target name.
While at it, use LOG_TARGET_xxx() for all log statements where the
target name is already used.
Change-Id: I70b134145837db623e008a4a6c0be0008d9a0d87
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8313
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Changes affect the function remote_bitbang_fill_buf.
When read_socket returns 0, socket reached EOF and there is
no data to read. But if request was blocking, the caller
expected some data. Such situations should be treated as ERROR.
Change-Id: I02ed484e61fb776c1625f6e36ab14c85891939b2
Signed-off-by: Timur Golubovich <timur.golubovich@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8325
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Commit f9509c92db ("itm: rework itm commands before 'init'")
ignores the default enable of ITM channel 0, that is applied when
no 'itm port[s]' is issued.
Call armv7m_trace_itm_config() unconditionally to handle it.
Change-Id: I3e85d0b063ed38c1552f6af9ea9eea2e76aa9025
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Paul Fertser <fercerpav@gmail.com>
Fixes: f9509c92db ("itm: rework itm commands before 'init'")
Reviewed-on: https://review.openocd.org/c/openocd/+/7900
Reviewed-by: <post@frankplowman.com>
Tested-by: jenkins
The register SPSR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL1
or through OpenOCD command
reg SPSR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8276
Tested-by: jenkins
The register ESR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5385200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL1
or through OpenOCD command
reg ESR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icd65470c279e5cfd03091db6435cdaa1c447644c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8275
Tested-by: jenkins
The register ELR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Without this patch, an error:
Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL1
or through OpenOCD command
reg ELR_EL1
Detect the EL and return error if the register cannot be accessed.
Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8274
Tested-by: jenkins
The register SPSR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns SPSR_EL1. Debugger should not
mix the real SPSR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL2
or through OpenOCD command
reg SPSR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8273
Tested-by: jenkins
The register ESR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ESR_EL1. Debugger should not mix
the real ESR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL2
or through OpenOCD command
reg ESR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icb32b44886d50907f29b068ce61e4be8bed10208
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8272
Tested-by: jenkins
The register ELR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ELR_EL1. Debugger should not mix
the real ELR_EL2 with the virtual register.
Without this patch, an error:
Error: Opcode 0xd53c4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL2
or through OpenOCD command
reg ELR_EL2
Detect the EL and return error if the register cannot be accessed.
Change-Id: Idf02b42a7339df83260c1e44ceabbb05fbf392b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8271
Tested-by: jenkins
The register SPSR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL3
or through OpenOCD command
reg SPSR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: I00849d99feeb96589c426fcafda98127dbd19a67
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8270
Tested-by: jenkins
The register ESR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL3
or through OpenOCD command
reg ESR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Drop the FIXME comment on Aarch32 case, as the register exists in
Aarch64 only.
Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8269
Tested-by: jenkins
The register ELR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Without this patch, an error:
Error: Opcode 0xd53e4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL3
or through OpenOCD command
reg ELR_EL3
Detect the EL and return error if the register cannot be accessed.
Change-Id: I545abb196e5c34e462c7e5d5d3ec952e588642da
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8268
Tested-by: jenkins
The command 'gdb_report_register_access_error' is used to silence
errors while reading registers and not reporting them to GDB.
Nevertheless, the error is printed by a LOG_ERROR() in armv8_dpm.
Change the message to LOG_DEBUG().
It will still cause the error to be propagated and eventually
printed by the caller (e.g. by the command 'reg').
Change-Id: Ic0db74fa28235d686ddd21a5960c52ae003e0931
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8267
Tested-by: jenkins
These functions are today always called with non-NULL parameter
regval, so the actual check is not needed.
Anyway, for any future code change, check the parameter at the
entry of the functions and return error if it is not valid.
Simplify the check to assign the result value and align the code
of the two functions.
Change-Id: Ie4d98063006d70d9e2bcfc00bc930133caf33515
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8266
Tested-by: jenkins
Use LOG_TARGET_ERROR() to print the error messages and additionally add
a reference to the related target.
Change-Id: I06722f3911ef4034fdd05dc9b0e2571b01b657a4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8314
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
cortex_m_poll_one() detects reset testing S_RESET_ST sticky bit.
If the signal comes unexpectedly, poll must return TARGET_RESET state.
On the contrary in case of polling inside of an OpenOCD reset command,
TARGET_RESET has been has already been set and we need to get out of
it as quickly as possible.
The original code needs 2 polls: the first clears S_RESET_ST
and keeps TARGET_RESET state, the current TARGET_RUNNING or TARGET_HALTED
is reflected as late as the second poll is done.
Change the logic to keep in TARGET_RESET only when necessary.
See also [1]
Link: [1] 8284: tcl/target: ti_cc3220sf: Use halt for CC3320SF targets | https://review.openocd.org/c/openocd/+/8284
Fixes: https://sourceforge.net/p/openocd/tickets/360/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I759461e5f89ca48a6e16e4b4101570260421dba1
Reviewed-on: https://review.openocd.org/c/openocd/+/8285
Tested-by: jenkins
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Remove list of id codes for all families.
Maintain a list with id, bscan-length and check position
in the tcl config files for each family.
The Intel FPGA Driver option 'family' is not otional anymore.
Change-Id: I9a40a041069e84f6b4728f2cd715756a36759c89
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/8083
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
In case of fail to allocate 'obj->name', the memory allocated for
'obj->out_filename' is not freed, thus leaking.
Since 'obj' is allocated with calloc(), thus zeroed, switch to use
the common error exit path for both allocations of 'obj->name' and
'obj->out_filename'.
Fixes: 2506ccb509 ("target/arm_tpiu_swo: Fix division by zero")
Change-Id: I412f66ddd7bf7d260cee495324058482b26ff0c5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8300
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Erase is initiated by write to a flash address. Due to the
silicon errata of nRF91 the write stalls the bus until the page erase
is finished (takes up to 87ms).
If the adapter does not handle SWD WAIT properly, the following read
in nrf5_wait_for_nvmc() returns ERROR_WAIT.
Wait for fixed time before accessing AP. Not nice, but the only
working solution until all adapters handle SWD WAIT.
If the fixed wait does not suffice, continue the wait loop after a delay.
It makes some unnecessary noise however erase works.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I63faf38dad79440a0117ed79930442bd2843c6db
Reviewed-on: https://review.openocd.org/c/openocd/+/8115
Reviewed-by: Tomáš Beneš <tomas@dronetag.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since nRF9160 Product Specification v2.1 the new UICR SIPINFO
fields should be preferred over UICR INFO.
Tested on nRF9161.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ib8005b3b6292aa20fa83c1dcebd2de27df58b661
Reviewed-on: https://review.openocd.org/c/openocd/+/8114
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Probes all flash and UICR areas.
Flash erase and write tested.
On nRF53 mass erase works on the application core flash bank only.
The Tcl script nrf53_recover can serve as the workaround on the
network core.
TODO: mass erase of the nRF53 network core flash.
Some ideas taken from [1] and [2].
Change-Id: I8e27a780f4d82bcabf029f79b87ac46cf6a531c7
Link: [1] 7404: flash: nor: add support for Nordic nRF9160 | https://review.openocd.org/c/openocd/+/7404
Link: [2] 8062: flash: nor: add support for Nordic nRF9160 | https://review.openocd.org/c/openocd/+/8062
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8112
Reviewed-by: Tomáš Beneš <tomas@dronetag.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Enable and disable erase mode only once
instead of toggling it for each sector.
Refactor to decrease the number of call levels.
Change-Id: Ie546a4fc24da0eea2753a2bebaa63d941ef7aa1d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8111
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Preparatory change before extending support to nRF53 and 91.
While on it, rename nRF51 and 52 specific routines and constants.
Change-Id: I46bc496cef5cbde46d6755a4b908c875351f6612
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8110
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For configurations which include multiple targets and the "pipe" mode is
requested only the first gdb_server instance should be enabled,
otherwise GDB gets confusing replies, goes out of sync and the session
fails in weird ways.
Compile-tested only.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: If8f13aa7b58e9b0dc6d5ae88cf75538b34cc1218
Reviewed-on: https://review.openocd.org/c/openocd/+/8222
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior
Change-Id: I67bafb1817c621a38ae4a2f55e12e4143e992c4e
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8296
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
LOG_USER only outputs to user interfaces, but leaves no way to get the
FTDI inputs over the RPC interface. Switch to command_print so this
string goes to both logs and the RPC interface.
Change-Id: I99024194b6687b88d354ef278aa25f372c862c22
Signed-off-by: Mark Featherston <mark@embeddedts.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8294
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
For some target, the API assert_reset() checks if the target has
been examined, with target_was_examined(), to perform conditional
operations like:
- assert adapter's srst;
- write some register to catch the reset vector;
- invalidate the register cache.
Targets created with -defer-examine gets the examine flag reset
right before entering in their assert_reset(), disrupting the
actions above.
For targets created with -defer-examine, move the reset examine
after the assert_reset().
Change-Id: If96e7876dcace8905165115292deb93a3e45cb36
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8293
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 236c54c94a ("server/gdb_server.c: support unavailable
registers") correctly returns a string of 'x' when the register is
not available in the current target.
While implementing this, it incorrectly drops the pre-existing
feature of optionally ignoring errors while reading a register.
This feature has a real use case documented in the OpenOCD manual
in chapter 'Using GDB as a non-intrusive memory inspector', where
GDB attaches to a target without halting it. For targets that need
to be halted to read its registers, we need to hack the values of
the registers returned to GDB; either returning 'xxxx' or an error
causes GDB to drop the connection.
Re-add the check on 'gdb_report_register_access_error' to keep the
pre-existing behavior when a register error has to be ignored:
- return a string of '0';
- drop a debug message.
Change-Id: Ie65c92f259f92502e688914f334655b635874179
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 236c54c94a ("server/gdb_server.c: support unavailable registers")
Reviewed-on: https://review.openocd.org/c/openocd/+/8228
Tested-by: jenkins
Few files include target_type.h even if it is not needed.
Drop the include.
Other files access directly to target type's name instead of using
the proper API target_type_name().
Use the API and drop the include.
Change-Id: I86c0e0bbad51db93500c0efa27b7d6f1a67a02c2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
clang doesn't support the gnu_printf attribute that OpenOCD uses if
__GNUC__ and __GNUC_MINOR__ indicates gcc >= 4.4.
Most clang builds set __GNUC__/__GNUC_MINOR__ to 4.2 for historical
reasons, so they don't trigger this condition; however, some builds set
it to something much higher to work around code using __GNUC__ to
determine if a feature that does exist in clang (but not gcc 4.2) is
available, causing OpenOCD to use attribute gnu_printf.
The problem can be reproduced without a special clang build by adding
-fgnuc-version=14.1 to CFLAGS.
Change-Id: I3c0832d4201578b116c5214203f95b6153dad30e
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8258
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Do not free the service in 'connection_closed_handler' because it is
free'd by the server infrastructure.
Checkpatch-ignore: COMMIT_LOG_LONG_LINE
This error was detected with valgrind:
==272468== Invalid free() / delete / delete[] / realloc()
==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x1F34C7: remove_service (server.c:374)
==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819)
==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x300000001: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== by 0x2: ???
==272468== Address 0x5fff650 is 0 bytes inside a block of size 24 free'd
==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x2ECA42: semihosting_service_connection_closed_handler (semihosting_common.c:1807)
==272468== by 0x1F2E39: remove_connection.isra.0 (server.c:164)
==272468== by 0x1F349E: remove_connections (server.c:350)
==272468== by 0x1F349E: remove_service (server.c:364)
==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819)
==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x300000001: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== Block was alloc'd at
==272468== at 0x484DA83: calloc (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x2ED326: handle_common_semihosting_redirect_command (semihosting_common.c:1931)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x400000002: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== by 0x2: ???
==272468==
Change-Id: I3e5323f145a98d1ff9ea7d03f87ed96140f49a18
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8257
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Currently, errors in pre/post-enable events are ignored and capturing is
always started, even if necessary device configuration fails. This
behaviour is confusing to users. Also, the TPIU must be disabled before
re-configuration is possible.
Start capturing and enable TPIU only if no errors in pre/post-enable
events occurred.
Change-Id: I422033e36ca006e38aa4504d491b7947def1237a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8254
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
When external capturing is configured (default), the SWO pin frequency
is required. Enforce this to avoid a division by zero error.
While at it, ensure that the 'out_filename' variable always contains a
valid string. This saves a few checks and makes the code more clean and
readable.
Change-Id: If8c1dae9549dd10e2f21d5b896414d47edac9fc2
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8224
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For MPU configs, determine memory access rights
by probing protection TLB. Issuing IHI without execute
permissions can trigger an exception.
No new clang static analyzer warnings.
Change-Id: Iea8eab5c2113df3f954285c3b9a79e96d41aa941
Signed-off-by: Ian Thompson <ianst@cadence.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8080
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Historically, the function cortex_a_dap_write_memap_register_u32()
was used to discriminate the register write in APB-AP CPU debug
against the complex memory access in AHB-AP memory bus.
It has no sense to keep the function and its comment.
Plus, by forcing atomic write it impacts the debug performance.
Drop it!
A further rework to enqueue sequence of atomic writes is needed.
Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8231
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
The command 'cache auto' was introduced with commit cd440bd32a
("add armv7a_cache handlers") in 2015 to allow disabling the cache
handling done automatically by OpenOCD.
This was probably a way to test the cache handling when there were
still the two independent accesses for APB-AP CPU debug and for
AHB-AP memory bus.
The handling of cache for cortex_a is robust and there is no more
reason to disable it.
The command 'cache auto' is not used in any upstream script.
On target aarch64 this command has never been introduced as the
cache is always handled automatically by OpenOCD.
Drop the command 'cache auto' and add it in the deprecated list.
Drop the flag 'auto_cache_enabled' by considering it as true.
Rename the function 'armv7a_cache_auto_flush_all_data()' as
'armv7a_cache_flush_all_data()' and, while there, fix the error
propagation in SMP case.
Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8230
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in
2009 but, due to lack of public documentation for ARMv7a, it was
almost a simple copy/paste from the existing code for Cortex-M
(ARMv7m).
On Cortex-M the same AP provides access to both CPU debug and CPU
memory. This feature is not present on ARMv7a.
To still keep some communality with ARMv7m code, the change [2]
splits the CPU debug access from the CPU memory access by using
two independent AP; this is copied from the system architecture of
TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on
AP#0, separated from AP#1 for the APB-AP CPU debug.
But the direct memory access through the system bus breaks the
coherency between memory and CPU caches, so change [3] added some
cache invalidation to avoid issues.
The code to allow ARMv7a CPU to really read/write in CPU memory
was added by change [4] in 2011. Such still not optimized
implementation was very slow, so it did not replace the access
through the system bus. A selection through DAP's 'apsel" command
was used to select between the two modes.
Only in 2015, with change [5], the speed of CPU read/write was
improved using the DCC_FAST_MODE. But the direct access to the
memory through the system bus remained.
Finally, with change [6] in 2018 the system bus access was dropped
for good, as the new virtual target "mem_ap" could implement such
access in a more clean way.
Only memory access through CPU remained for ARMv7a.
Nevertheless, a useless cache invalidation remained in the code,
decreasing the speed of the write access.
Drop the useless cache invalidate on CPU memory write and the
associated comment, not anymore valid.
Drop the now unused function armv7a_cache_auto_flush_on_write().
This provides a speedup of between 4 and 8, depending on adapter
and JTAG/SWD speed.
Link: [1] 7a93100c2d ("Add minimalist Cortex A8 file")
Link: [2] 1d0b276c9f ("The rest of the Cortex-A8 support from Magnus: ...")
Link: [3] d4e4d65d28 ("Cache invalidation when writing to memory")
Link: [4] 05ab8bdb81 ("cortex_a9: implement read/write memory through APB-AP")
Link: [5] 0228f8e827 ("Cortex A: fix extra memory read and non-word sizes")
Link: [6] fac9be64d9 ("target/cortex_a: remove buggy memory AP accesses")
Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8229
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Fix possible double free and possible
memory leak while creating an ipdbg hub.
Change-Id: I6254663c27c4f38d46008c4dbff11aa27b84f399
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/8085
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The gdb subsystem is initialized after the first target examine,
so the field struct target::gdb_service is NULL during examine.
A command "smp off" in the examine event handler causes a SIGSEGV
during OpenOCD startup.
Check for pointer not NULL before dereferencing it.
Change-Id: Id115e28be23a957fef1b97ab66d7273f0ea0dce4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8216
Tested-by: jenkins
The code for cortex_a allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8215
Tested-by: jenkins
The code for aarch64 allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: Ie13abb0ae2cc28fc3295d678c4ad1691024eb7b8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8214
Tested-by: jenkins
Prevent a segmentation fault by preventing to try to halt a target
that has not been examined yet.
Change-Id: I5d344e7fbdb5422f7c5e2c39bdd48cbc6c2a3e58
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8213
Tested-by: jenkins
Commit 16b4b8cf54 ("Cortex-M3: expose most DWT registers") added
the DWT registers to the list of CPU registers.
The commit message from 2009 reports the reason behind this odd
mixing of CPU and DWT registers.
This feature got broken in 2017 with the introduction of the field
struct reg::exist and its further use in the code. As result, the
command 'reg' on a target Cortex-M reports only the core registers
and then the header line
===== Cortex-M DWT registers
not anymore followed by the DWT registers.
Fix it by tagging each DWT registers as existing.
Change-Id: Iab026e7da8d6b8ba052514c3fd3b5cdfe301f330
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b5964191f0 ("register: support non-existent registers")
Reviewed-on: https://review.openocd.org/c/openocd/+/8198
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Checkpatch complains for extra parenthesis not required.
Drop them.
Change-Id: I311409f5732acf10a4910de5dcf0fb05f43e21b5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8187
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Initialized `value` variables that could only be set in a branch.
Change-Id: Iec7413ade9d053c93352a58ff954ad49a6545923
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8179
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Karl Palsson
Richard Allen
Marc Schink
Peter Collingbourne
Antonio Borneo
Grant Ramsay
Tarek BOCHKATI
Tarek BOCHKATI
Evgeniy Naydanov
Jonathan Forrest
Jan Matyas
Tomas Vanek
Ian Thompson
Mark Zhuang
Timur Golubovich
Daniel Anselmi
Paul Fertser
Parshintsev Anatoly
Mark Featherston
Noah Moroze
Bernhard Rosenkränzer
Walter Ji