flash/nor/nrf5: introduce address maps
Preparatory change before extending support to nRF53 and 91. While on it, rename nRF51 and 52 specific routines and constants. Change-Id: I46bc496cef5cbde46d6755a4b908c875351f6612 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8110 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek
parent
ed9203f4aa
commit
37f9485cef
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@ -19,8 +19,7 @@
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#include <helper/time_support.h>
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#include <helper/bits.h>
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/* Both those values are constant across the current spectrum ofr nRF5 devices */
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#define WATCHDOG_REFRESH_REGISTER 0x40010600
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/* The refresh code is constant across the current spectrum of nRF5 devices */
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#define WATCHDOG_REFRESH_VALUE 0x6e524635
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enum {
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@ -28,12 +27,9 @@ enum {
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};
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enum nrf5_ficr_registers {
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NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
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NRF51_52_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
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#define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
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NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
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NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
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#define NRF5_FICR_REG(offset) (NRF51_52_FICR_BASE + (offset))
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NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
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NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
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@ -42,39 +38,23 @@ enum nrf5_ficr_registers {
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NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
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NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
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NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
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/* CONFIGID is documented on nRF51 series only.
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* On nRF52 is present but not documented */
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NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
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/* Following registers are available on nRF52 and on nRF51 since rev 3 */
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NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
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NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
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NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
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NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
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NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
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};
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enum nrf5_uicr_registers {
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NRF5_UICR_BASE = 0x10001000, /* User Information
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NRF51_52_UICR_BASE = 0x10001000, /* User Information
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* Configuration Registers */
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#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
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#define NRF5_UICR_REG(offset) (NRF51_52_UICR_BASE + (offset))
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NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
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};
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enum nrf5_nvmc_registers {
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NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
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* Controller Registers */
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#define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
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NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
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NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
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NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
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NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
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NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
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NRF5_NVMC_READY = 0x400,
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NRF5_NVMC_CONFIG = 0x504,
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NRF5_NVMC_ERASEPAGE = 0x508,
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NRF5_NVMC_ERASEALL = 0x50C,
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NRF5_NVMC_ERASEUICR = 0x514,
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NRF5_BPROT_BASE = 0x40000000,
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};
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@ -110,6 +90,28 @@ struct nrf5_device_spec {
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enum nrf5_features features;
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};
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/* FICR registers offsets */
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struct nrf5_ficr_map {
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uint32_t codepagesize;
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uint32_t codesize;
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uint32_t configid;
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uint32_t info_part;
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uint32_t info_variant;
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uint32_t info_package;
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uint32_t info_ram;
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uint32_t info_flash;
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};
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/* Map of device */
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struct nrf5_map {
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uint32_t flash_base;
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uint32_t ficr_base;
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uint32_t uicr_base;
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uint32_t nvmc_base;
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uint32_t watchdog_refresh_addr;
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};
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struct nrf5_info {
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unsigned int refcount;
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@ -127,6 +129,9 @@ struct nrf5_info {
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enum nrf5_features features;
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unsigned int flash_size_kb;
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unsigned int ram_size_kb;
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const struct nrf5_map *map;
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const struct nrf5_ficr_map *ficr_offsets;
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};
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#define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
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@ -238,6 +243,31 @@ static const struct nrf5_device_package nrf52_packages_table[] = {
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{ 0x2009, "CF" },
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};
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static const struct nrf5_ficr_map nrf51_52_ficr_offsets = {
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.codepagesize = 0x10,
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.codesize = 0x14,
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/* CONFIGID is documented on nRF51 series only.
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* On nRF52 is present but not documented */
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.configid = 0x5c,
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/* Following registers are available on nRF52 and on nRF51 since rev 3 */
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.info_part = 0x100,
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.info_variant = 0x104,
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.info_package = 0x108,
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.info_ram = 0x10c,
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.info_flash = 0x110,
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};
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static const struct nrf5_map nrf51_52_map = {
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.flash_base = NRF5_FLASH_BASE,
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.ficr_base = NRF51_52_FICR_BASE,
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.uicr_base = NRF51_52_UICR_BASE,
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.nvmc_base = 0x4001E000,
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.watchdog_refresh_addr = 0x40010600,
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};
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const struct flash_driver nrf5_flash, nrf51_flash;
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static bool nrf5_bank_is_probed(const struct flash_bank *bank)
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@ -248,6 +278,24 @@ static bool nrf5_bank_is_probed(const struct flash_bank *bank)
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return nbank->probed;
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}
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static bool nrf5_bank_is_uicr(const struct nrf5_bank *nbank)
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{
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struct nrf5_info *chip = nbank->chip;
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assert(chip);
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return nbank == &chip->bank[1];
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}
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static int nrf5_nvmc_read_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t *value)
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{
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return target_read_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
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}
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static int nrf5_nvmc_write_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t value)
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{
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return target_write_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
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}
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static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
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{
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uint32_t ready;
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@ -256,7 +304,7 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
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int64_t ts_start = timeval_ms();
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do {
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res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
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res = nrf5_nvmc_read_u32(chip, NRF5_NVMC_READY, &ready);
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if (res != ERROR_OK) {
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LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
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return res;
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@ -276,7 +324,7 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
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static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
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{
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int res;
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res = target_write_u32(chip->target,
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res = nrf5_nvmc_write_u32(chip,
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NRF5_NVMC_CONFIG,
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NRF5_NVMC_CONFIG_EEN);
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@ -299,7 +347,7 @@ static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
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static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
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{
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int res;
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res = target_write_u32(chip->target,
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res = nrf5_nvmc_write_u32(chip,
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NRF5_NVMC_CONFIG,
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NRF5_NVMC_CONFIG_WEN);
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@ -322,7 +370,7 @@ static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
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static int nrf5_nvmc_read_only(struct nrf5_info *chip)
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{
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int res;
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res = target_write_u32(chip->target,
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res = nrf5_nvmc_write_u32(chip,
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NRF5_NVMC_CONFIG,
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NRF5_NVMC_CONFIG_REN);
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@ -350,7 +398,7 @@ static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
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if (res != ERROR_OK)
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goto error;
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res = target_write_u32(chip->target,
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res = nrf5_nvmc_write_u32(chip,
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erase_register,
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erase_value);
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if (res != ERROR_OK)
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@ -370,7 +418,8 @@ error:
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return ERROR_FAIL;
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}
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static int nrf5_protect_check_clenr0(struct flash_bank *bank)
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/* nRF51 series only */
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static int nrf51_protect_check_clenr0(struct flash_bank *bank)
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{
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int res;
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uint32_t clenr0;
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@ -403,7 +452,8 @@ static int nrf5_protect_check_clenr0(struct flash_bank *bank)
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return ERROR_OK;
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}
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static int nrf5_protect_check_bprot(struct flash_bank *bank)
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/* nRF52 series only */
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static int nrf52_protect_check_bprot(struct flash_bank *bank)
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{
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struct nrf5_bank *nbank = bank->driver_priv;
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assert(nbank);
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@ -432,26 +482,27 @@ static int nrf5_protect_check_bprot(struct flash_bank *bank)
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static int nrf5_protect_check(struct flash_bank *bank)
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{
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/* UICR cannot be write protected so just return early */
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if (bank->base == NRF5_UICR_BASE)
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return ERROR_OK;
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struct nrf5_bank *nbank = bank->driver_priv;
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assert(nbank);
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struct nrf5_info *chip = nbank->chip;
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assert(chip);
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/* UICR cannot be write protected so just return early */
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if (nrf5_bank_is_uicr(nbank))
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return ERROR_OK;
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if (chip->features & NRF5_FEATURE_BPROT)
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return nrf5_protect_check_bprot(bank);
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return nrf52_protect_check_bprot(bank);
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if (chip->features & NRF5_FEATURE_SERIES_51)
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return nrf5_protect_check_clenr0(bank);
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return nrf51_protect_check_clenr0(bank);
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LOG_WARNING("Flash protection of this nRF device is not supported");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
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/* nRF51 series only */
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static int nrf51_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
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unsigned int last)
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{
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int res;
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@ -517,8 +568,13 @@ error:
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static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
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unsigned int last)
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{
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struct nrf5_bank *nbank = bank->driver_priv;
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assert(nbank);
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struct nrf5_info *chip = nbank->chip;
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assert(chip);
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/* UICR cannot be write protected so just bail out early */
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if (bank->base == NRF5_UICR_BASE) {
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if (nrf5_bank_is_uicr(nbank)) {
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LOG_ERROR("UICR page does not support protection");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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@ -528,13 +584,8 @@ static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
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return ERROR_TARGET_NOT_HALTED;
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}
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struct nrf5_bank *nbank = bank->driver_priv;
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assert(nbank);
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struct nrf5_info *chip = nbank->chip;
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assert(chip);
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if (chip->features & NRF5_FEATURE_SERIES_51)
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return nrf5_protect_clenr0(bank, set, first, last);
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return nrf51_protect_clenr0(bank, set, first, last);
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LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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@ -564,7 +615,7 @@ static const char *nrf5_decode_info_package(uint32_t package)
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return "xx";
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}
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static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
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static int nrf5_get_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
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{
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int res;
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if (chip->spec) {
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@ -597,7 +648,7 @@ static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
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assert(chip);
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char chip_type_str[256];
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if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
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if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
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return ERROR_FAIL;
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command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
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@ -605,14 +656,16 @@ static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
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return ERROR_OK;
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}
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static int nrf5_read_ficr_info(struct nrf5_info *chip)
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static int nrf5_read_ficr_info(struct nrf5_info *chip, const struct nrf5_map *map,
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const struct nrf5_ficr_map *ficr_offsets)
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{
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int res;
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struct target *target = chip->target;
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uint32_t ficr_base = map->ficr_base;
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chip->ficr_info_valid = false;
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res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
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res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part);
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if (res != ERROR_OK) {
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LOG_DEBUG("Couldn't read FICR INFO.PART register");
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return res;
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@ -655,19 +708,19 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
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* VARIANT and PACKAGE coding is unknown for a nRF51 device.
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* nRF52 devices have FICR INFO documented and always filled. */
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res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
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res = target_read_u32(target, ficr_base + ficr_offsets->info_variant, &chip->ficr_info.variant);
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if (res != ERROR_OK)
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return res;
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res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
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res = target_read_u32(target, ficr_base + ficr_offsets->info_package, &chip->ficr_info.package);
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if (res != ERROR_OK)
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return res;
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res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
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res = target_read_u32(target, ficr_base + ficr_offsets->info_ram, &chip->ficr_info.ram);
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if (res != ERROR_OK)
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return res;
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res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
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res = target_read_u32(target, ficr_base + ficr_offsets->info_flash, &chip->ficr_info.flash);
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if (res != ERROR_OK)
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return res;
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@ -675,7 +728,8 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
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return ERROR_OK;
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}
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static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
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/* nRF51 series only */
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static int nrf51_get_ram_size(struct target *target, uint32_t *ram_size)
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{
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int res;
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@ -718,24 +772,33 @@ static int nrf5_probe(struct flash_bank *bank)
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assert(chip);
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struct target *target = chip->target;
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uint32_t configid;
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res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
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chip->spec = NULL;
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/* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
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chip->features = NRF5_FEATURE_SERIES_51;
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chip->map = &nrf51_52_map;
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chip->ficr_offsets = &nrf51_52_ficr_offsets;
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/* Don't bail out on error for the case that some old engineering
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* sample has FICR INFO registers unreadable. We can proceed anyway. */
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(void)nrf5_read_ficr_info(chip, chip->map, chip->ficr_offsets);
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|
||||
const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets;
|
||||
uint32_t ficr_base = chip->map->ficr_base;
|
||||
uint32_t configid = 0;
|
||||
res = target_read_u32(target, ficr_base + ficr_offsets->configid, &configid);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Couldn't read CONFIGID register");
|
||||
return res;
|
||||
if (chip->features & NRF5_FEATURE_SERIES_51) {
|
||||
LOG_ERROR("Couldn't read FICR CONFIGID register");
|
||||
return res;
|
||||
}
|
||||
|
||||
LOG_DEBUG("Couldn't read FICR CONFIGID register, using FICR INFO");
|
||||
}
|
||||
|
||||
/* HWID is stored in the lower two bytes of the CONFIGID register */
|
||||
chip->hwid = configid & 0xFFFF;
|
||||
|
||||
/* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
|
||||
chip->features = NRF5_FEATURE_SERIES_51;
|
||||
|
||||
/* Don't bail out on error for the case that some old engineering
|
||||
* sample has FICR INFO registers unreadable. We can proceed anyway. */
|
||||
(void)nrf5_read_ficr_info(chip);
|
||||
|
||||
chip->spec = NULL;
|
||||
for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
|
||||
if (chip->hwid == nrf5_known_devices_table[i].hwid) {
|
||||
chip->spec = &nrf5_known_devices_table[i];
|
||||
|
|
@ -753,15 +816,17 @@ static int nrf5_probe(struct flash_bank *bank)
|
|||
|
||||
if (chip->ficr_info_valid) {
|
||||
chip->ram_size_kb = chip->ficr_info.ram;
|
||||
} else {
|
||||
} else if (chip->features & NRF5_FEATURE_SERIES_51) {
|
||||
uint32_t ram_size;
|
||||
nrf5_get_ram_size(target, &ram_size);
|
||||
nrf51_get_ram_size(target, &ram_size);
|
||||
chip->ram_size_kb = ram_size / 1024;
|
||||
} else {
|
||||
chip->ram_size_kb = 0;
|
||||
}
|
||||
|
||||
/* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
|
||||
/* The value stored in FICR CODEPAGESIZE is the number of bytes in one page of FLASH. */
|
||||
uint32_t flash_page_size;
|
||||
res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
|
||||
res = target_read_u32(chip->target, ficr_base + ficr_offsets->codepagesize,
|
||||
&flash_page_size);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Couldn't read code page size");
|
||||
|
|
@ -769,9 +834,10 @@ static int nrf5_probe(struct flash_bank *bank)
|
|||
}
|
||||
|
||||
/* Note the register name is misleading,
|
||||
* NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
|
||||
* FICR CODESIZE is the number of pages in flash memory, not the number of bytes! */
|
||||
uint32_t num_sectors;
|
||||
res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
|
||||
res = target_read_u32(chip->target, ficr_base + ficr_offsets->codesize,
|
||||
&num_sectors);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Couldn't read code memory size");
|
||||
return res;
|
||||
|
|
@ -781,7 +847,7 @@ static int nrf5_probe(struct flash_bank *bank)
|
|||
|
||||
if (!chip->bank[0].probed && !chip->bank[1].probed) {
|
||||
char chip_type_str[256];
|
||||
if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
|
||||
if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
|
||||
LOG_INFO("%s%s %ukB Flash, %ukB RAM",
|
||||
|
|
@ -793,7 +859,7 @@ static int nrf5_probe(struct flash_bank *bank)
|
|||
|
||||
free(bank->sectors);
|
||||
|
||||
if (bank->base == NRF5_FLASH_BASE) {
|
||||
if (bank->base == chip->map->flash_base) {
|
||||
/* Sanity check */
|
||||
if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
|
||||
LOG_WARNING("Chip's reported Flash capacity does not match expected one");
|
||||
|
|
@ -810,6 +876,7 @@ static int nrf5_probe(struct flash_bank *bank)
|
|||
chip->bank[0].probed = true;
|
||||
|
||||
} else {
|
||||
/* UICR bank */
|
||||
bank->num_sectors = 1;
|
||||
bank->size = flash_page_size;
|
||||
|
||||
|
|
@ -849,7 +916,7 @@ static int nrf5_erase_page(struct flash_bank *bank,
|
|||
|
||||
LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
|
||||
|
||||
if (bank->base == NRF5_UICR_BASE) {
|
||||
if (bank->base == chip->map->uicr_base) {
|
||||
if (chip->features & NRF5_FEATURE_SERIES_51) {
|
||||
uint32_t ppfc;
|
||||
res = target_read_u32(chip->target, NRF51_FICR_PPFC,
|
||||
|
|
@ -958,7 +1025,7 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
|
|||
buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
|
||||
buf_set_u32(reg_params[3].value, 0, 32, address);
|
||||
buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
|
||||
buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
|
||||
buf_set_u32(reg_params[5].value, 0, 32, chip->map->watchdog_refresh_addr);
|
||||
|
||||
retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
|
||||
0, NULL,
|
||||
|
|
@ -1008,7 +1075,7 @@ static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
* is protected. */
|
||||
if (chip->features & NRF5_FEATURE_SERIES_51) {
|
||||
|
||||
res = nrf5_protect_check_clenr0(bank);
|
||||
res = nrf51_protect_check_clenr0(bank);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
|
|
@ -1065,7 +1132,7 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
|
|||
* is protected. */
|
||||
if (chip->features & NRF5_FEATURE_SERIES_51) {
|
||||
|
||||
res = nrf5_protect_check_clenr0(bank);
|
||||
res = nrf51_protect_check_clenr0(bank);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
|
|
@ -1136,7 +1203,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
|
|||
|
||||
switch (bank->base) {
|
||||
case NRF5_FLASH_BASE:
|
||||
case NRF5_UICR_BASE:
|
||||
case NRF51_52_UICR_BASE:
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
|
||||
|
|
@ -1157,7 +1224,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
|
|||
case NRF5_FLASH_BASE:
|
||||
nbank = &chip->bank[0];
|
||||
break;
|
||||
case NRF5_UICR_BASE:
|
||||
case NRF51_52_UICR_BASE:
|
||||
nbank = &chip->bank[1];
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue