Commit Graph

11399 Commits

Author SHA1 Message Date
Tim Newsome 2f1714789b
Merge pull request #921 from lz-bro/repeat_read-fix
target/riscv: support riscv repeat_read by sysbus access
2023-09-29 09:31:59 -07:00
Tim Newsome 75b5de67df
Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreak
openocd does not allow to query status of dcsr.ebreak{u,s,m}
2023-09-29 09:30:46 -07:00
Tim Newsome ef3be96ba1
Merge pull request #892 from en-sc/en-sc/register-printing
target/riscv: define register printers
2023-09-28 08:36:36 -07:00
Kirill Radkin ee2bc807eb openocd does not allow to query status of dcsr.ebreak{u,s,m}
Extend riscv set_ebreak* commands.
Now it can be called without args to print current value.

riscv_ebreak* flags are moved to riscv_info struct.

Change-Id: Ib46e6b6dfc0117599c7f6715c7aaf113e63bd7dc
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-26 11:52:30 +03:00
Tim Newsome b5e57e1894
Merge pull request #913 from riscv/from_upstream
From upstream
2023-09-25 09:21:09 -07:00
Evgeniy Naydanov 43ebdd47a5 target/riscv: define register printers
`riscv_debug_reg_to_s()` can be used to decode register value.  If the
pointer to buffer is `NULL` it does not print anything, just returns the
length of the string.

The format is:
`<register_value> { <field_name>=<field_value_name or field_value>, ..., }`

e.g:

`0x400382 { version=2, ... ndmresetpending=false, }`

`0x321009 { regno=0x1009, ... cmdtype=0, }`

Change-Id: I63733d8d36385d89ca15de1a43139134bc488c4f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-22 16:26:28 +03:00
liangzhen a8ffda6e70 target/riscv: support riscv repeat_read by sysbus access
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-09-21 15:33:17 +08:00
Tim Newsome 2427f585c9
Merge pull request #916 from riscv/getreg_assert
target/riscv: Don't assert in riscv013_get_register()
2023-09-14 11:37:01 -07:00
Tim Newsome 2c2135a0cb target/riscv: Don't assert in riscv013_get_register()
When the target isn't halted, simply return an error. This used to be
purely internal code so an assert was appropriate. Now after some
refactoring and with unavailable harts you could get here when the hart
is unavailable. In that case the right thing is simply to return an
error message.

Change-Id: I49d26a11fe7565c645fd2480e89a2c35ea9b1688
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-13 13:44:20 -07:00
Tim Newsome fb26f4f89d target/xtensa: Fix build warning.
Change-Id: I9ee69807bec729480dd94da874fe1771d8f06078
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-12 13:11:05 -07:00
Tim Newsome 8c1f1b77d3 Merge commit 'ee31f1578a333a75737bc5b183cd4ae98cdaf798' into from_upstream
Conflicts:
	Makefile.am
	jimtcl
	src/helper/Makefile.am
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/rtos/rtos_standard_stackings.c

Change-Id: I00c98d20089558744988184370a8cb7f95f03329
2023-09-12 12:55:10 -07:00
Tim Newsome 67c2835997
Merge pull request #911 from riscv/from_upstream
From upstream
2023-09-11 12:53:42 -07:00
Tim Newsome 53f21336c4
Merge pull request #912 from MarekVCodasip/make-unknown-semihosting-error
target/riscv_semihosting: Make the unknown operation number an error
2023-09-08 09:22:10 -07:00
Tim Newsome 42dcc99026
Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggers
target/riscv: cleanup riscv_enumerate_triggers()
2023-09-08 09:21:55 -07:00
Tim Newsome 54372dd5a6
Merge pull request #908 from MarekVCodasip/disable-soft-bp-size-2-non-compressed
target/riscv: Reject size 2 soft breakpoints when C extension not supported
2023-09-07 10:03:36 -07:00
Evgeniy Naydanov c286f938f4 target/riscv: cleanup riscv_enumerate_triggers()
1. Propagate error codes.
2. Disable leftover triggers in case `tinfo` is supported.

Change-Id: Ie20edb4d8b9245e13ac8757bf6afe549ac99c4f1
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-07 13:39:50 +03:00
Marek Vrbka 1936dbd6cf target/riscv_semihosting: Make the unknown operation number an error
Previously, an unknown semihosting operation number
was logged as debug. This patch changes it and few
other places to be logged as error instead.

Change-Id: I83cae5ca1e3daed440f92b08bd372bfffbbad63c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-07 08:08:06 +02:00
Marek Vrbka 8ad41767c0 target/riscv: Reject size 2 soft breakpoints when C extension not supported
This patch disables software breakpoints of size 2 for targets
which don't support compressed instructions.

Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04 07:47:03 +02:00
Tim Newsome 699eecaab4
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
2023-08-30 10:59:54 -07:00
Tim Newsome 0801c66ff4 Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstream
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
2023-08-29 13:10:44 -07:00
Tim Newsome 5efea16944
Merge pull request #900 from aap-sc/aap-sc/simplify_state_managment
riscv: simplify state management during examine
2023-08-29 10:11:52 -07:00
Marek Vrbka 0b914fe5ae target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-25 07:54:59 +02:00
Tim Newsome 928f2b374a
Merge pull request #904 from kr-sc/kr-sc/support-sv57
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23 12:03:21 -07:00
Tim Newsome 7aedb15951
Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_running
fix crash when we try to read vector register on a running target
2023-08-23 12:01:49 -07:00
Tim Newsome 5cb60e3f7d
Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
2023-08-18 09:32:51 -07:00
Parshintsev Anatoly 198edca6d0 riscv: simplify state management during examine
This also fixes a bug when, after `examine` completion, the target still
has  `unknown` status. To reproduce this one spike, it is enough to do
the following:

---
// make sure spike harts are halted
openocd ... -c init -c 'echo "[targets]"'
---

this behavior is quite dangerous and leads to segfaults in some cases

Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 15:29:19 +03:00
Parshintsev Anatoly 0ae47ae472 fix crash when we try to read vector register on a running target
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 00:18:10 +03:00
Tim Newsome f061623568
Merge pull request #901 from aap-sc/aap-sc/refactor_reg_rw_progbuf
[riscv] refactor functions that register read/write via progbuf
2023-08-17 09:27:28 -07:00
Xiang W 373b8f1a89 target/riscv: fix execute_fence
This patch improves the following issues:
1. Makes it compatible with targets with progbufsize == 1.
2. Although exceptions don’t update any registers, but  do end execution
of the progbuf. This will make fence rw, rw impossible to execute.

Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6
Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-17 09:05:36 +08:00
Parshintsev Anatoly a8fedebcb4 [riscv] refactor functions that register read/write via progbuf
The motivation for this refactor is to fixup error handling for some
corner cases. These functions attempt to cache S0 register and only then
perform a bunch of extra checks to figure out if the requested register
is valid one in this context. The problem is that there are few corner
cases when _*progbuf functions could receive a GPR as an input. For
example, an abstract read could fail (for whatever reason) leading to
infinite recursion:

````
save S0 -> read S0 -> save S0 -> read S0 -> ...
```

The case described above could be fixed by adding extra sanitity checks,
however I decided to make these functions more modular since I find
self-contained functions easier to read.

Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-15 17:54:00 +03:00
Tim Newsome 9260101307
Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlbl
target/riscv: improve error handling in trigger setup
2023-08-14 09:48:03 -07:00
Tim Newsome 68ad364f27
Merge pull request #897 from aap-sc/aap-sc/wp_data_not_implemented
add diagnostics for non-implemented data watchpoints
2023-08-14 09:43:24 -07:00
Kirill Radkin 1d2eea0399 target/riscv: Add support for Sv57 translation mode (including second-stage translations)
Also fix Sv48x4 translation mode
2023-08-14 14:33:44 +03:00
Evgeniy Naydanov 9b558838b1 target/riscv: improve error handling in trigger setup
Change-Id: I235973a3c44fb3d934925c74ffee47f8bd96de0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-08-03 17:58:16 +03:00
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Tim Newsome ee5c5c292f
Merge pull request #895 from kr-sc/kr-sc/reset-fails-with-assert
target/riscv: OpenOCD fails with assert during running "reset" command
2023-08-01 09:10:41 -07:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Tim Newsome 1997e68dcb
Merge pull request #875 from zqb-all/support_multiple_DMs
target/riscv: support multiple DMs
2023-07-27 08:44:34 -07:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Tim Newsome aeb37cb461
Merge pull request #882 from MarekVCodasip/target-logging-usage
target/riscv: Add target name logging to most log prints.
2023-07-24 08:59:06 -07:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Tim Newsome 21fd3e1d6c
Merge pull request #885 from erhankur/fix_tool_warnings
Fix Checkpatch and Sparse tool warnings
2023-07-21 09:12:55 -07:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Erhan Kurubas e6f30aef80 src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-20 23:09:06 +02:00
Tim Newsome 1a089d8409
Merge pull request #888 from MarekVCodasip/ci-run-spike64-if-spike32-failed
github/ci Make Spike64-2 tests run regardless of Spike32 tests result
2023-07-20 12:09:20 -07:00
Tim Newsome c1cce47933
Merge pull request #886 from erhankur/update_espressif_chips
Update espressif chips
2023-07-20 12:06:59 -07:00
Tim Newsome fba957ab8e
Merge pull request #891 from riscv/cache_master
Run spike tests on `riscv` branch.
2023-07-19 11:15:29 -07:00