Commit Graph

6266 Commits

Author SHA1 Message Date
Tim Newsome 0ff4103a26 Reset address if target was busy during bust write
Improve Issue .

DebugCompareSections is still failing for me (with an instrumented
sometimes-slow spike), but MemTestBlock now passes reliably.
2017-08-15 15:47:35 -07:00
Tim Newsome 5c39079a62 Remove some unnecessary casts. 2017-08-15 14:29:24 -07:00
Tim Newsome 5092f96105 Add some keep_alive()s for use with slow targets. 2017-08-15 13:31:06 -07:00
Tim Newsome 0d74c8689d Fix block memory reads on slow targets.
The interesting new code concerns ignore_prev_addr and
this_is_last_read.

Additionally, I tweaked some debug output, and optimized
riscv_batch_run() when the batch is empty.
2017-08-14 15:02:19 -07:00
Tim Newsome 2706df0ec3 Fix a corner case in block memory read. 2017-08-13 14:14:23 -07:00
Gleb Gagarin 3109da7dfd Force actual read from prog buffer for the last transaction in read_memory() 2017-08-12 14:51:12 -07:00
Gleb Gagarin e676d3dae6 Fixed off-by-one error in previous commit 2017-08-11 17:46:35 -07:00
Gleb Gagarin 39b01259fa fixed memory leak introduced by previous commit 2017-08-10 16:37:50 -07:00
Gleb Gagarin b5692585de Fix reads beyond requested memory range 2017-08-10 14:27:11 -07:00
Andreas Bolsch 7719e9618e Support for STM32F722, F723, F413 and F423
IDs for STM32F722, F723, F413 and F423 added, handling of PCROP
for F722/723 and additional nWPRT bits for F413/423 implemented.
The additional protection bit positions for F413/423 conflict
with other options bits for the F7xx variants, additionally the
last two sectors share a common bit.

Protection for F413 and F767/777 now use protection blocks
rather sectors for dealing with protections bits.

Checking for halted state in 'lock' and 'unlock' removed: When
PCROP is activated in F723, halted state is not detected properly,
but lock/unlock sequence is required to disable PCROP.

Tested with STM32F723E-Disco, STM32F413ZH-Nucleo.

Change-Id: Ie6ddab47a9ae8461087d369b4f289b7f9d1e031c
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4045
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-10 09:35:47 +01:00
Andreas Fritiofson 3ee81fd787 log: Add a new debug level (4) for verbose I/O debug
Change ftdi SWD driver and CMSIS-DAP to use it instead of LOG_DEBUG().

Change-Id: I17ba3de2086c7159209db61fba3faf067dfc5023
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3805
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-08-10 09:29:06 +01:00
Karl Palsson 04b23ef502 stm32l1: Devid 0x429 only has 8bit flash size register
A footnote in RM0038r14.

Change-Id: Ic31894d846fbbe917a7290b2b7ff8fb582bb65da
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4198
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-08-10 09:20:39 +01:00
Tim Newsome efcfcf555f Fix assertion failure when reading from address 0. 2017-08-09 12:42:17 -07:00
Tim Newsome b897807224 When gdb_port is 0, don't increment it.
Usually incrementing to get the next port is a good idea, but when set
to 0 the idea is to find an arbitrary unallocated port. 1 is almost
certainly not helpful.
2017-08-07 13:55:37 -07:00
Tim Newsome 46b5f913c7 Display register numbers in a more usable format. 2017-07-27 13:45:26 -07:00
Tim Newsome 753d15e22c Print out which port OpenOCD is listening on.
This is essential when a test environment asks OpenOCD to listen on port
0, so that the environment can easily discover which port is actually
being used.
2017-07-25 14:08:10 -07:00
Tomas Vanek 02bc718d1a flash Kinetis: fix probe for FlexNVM partitioned as EEPROM backup
If a MCU has FlexNVM partitioned as EEPROM backup only
(no data flash), kinetis_probe_chip() detects zero fcfg2_maxaddr1
and adjusts flash banks count to 1, what is obviously wrong.

The change limits the test to devices without FlexNVM.

Computation of program flash/FlexNVM blocks is now more robust.

Missing case 0x07 is added to switch (fcfg1_depart)

Change-Id: I0bd6030a0fe1ab62aeb0223bbdf2aee1505bf6a0
Reported-by: simon.haines@scalardata.com
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4180
Tested-by: jenkins
Reviewed-by: Simon Haines <simon.haines@scalardata.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-07-24 13:11:06 +01:00
Tomas Vanek dbd0d90af9 flash Kinetis: fix devices with smallest program flash (8 and 16 kB)
Change-Id: I2692b9877a7f877104528f279a69e8cc1cfbcdbf
Reported-by: David Miller Lowe <milhead@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4173
Tested-by: jenkins
Reviewed-by: Miller Lowe <miller.lowe@trailtech.net>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-07-24 13:09:37 +01:00
Tim Newsome b032eb1bcc Use a wall clock timeout to complete reset. 2017-07-16 11:48:12 -07:00
Tim Newsome f0f1df1061 Fix infinite loop in reset. 2017-07-14 12:50:11 -07:00
Tim Newsome d60dbd60e8 Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
Tim Newsome 2deb02695e Forgot to commit this follow up to PR 2017-07-12 17:51:38 -07:00
Tim Newsome 09bf86e31a Keep around cmderr for callers to inspect.
Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
Tim Newsome 856f70fe44 Try abstract register writes as well. 2017-07-12 14:13:31 -07:00
Tim Newsome f37e93bbc0 Try using abstract commands to read registers
This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.

Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).

riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
Tim Newsome da74f511b9 Merge pull request from riscv/triggers
Disable debugger-set triggers on connect
2017-07-11 12:13:56 -07:00
Palmer Dabbelt 10a61000b5 Use LL for 64-bit defines, as Windows is LLP64
This should also fix bugs on ILP32 systems.
2017-07-10 13:45:42 -07:00
Tim Newsome 4072fa493b Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
Andreas Fritiofson 29cfe9c5ee mips32: inline functions in headers must be static
Change-Id: If1d0fc6766cadc2db33408ae5c0968de6b7a1b94
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4178
Tested-by: jenkins
Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-by: Stian Skjelstad <stian@nixia.no>
2017-07-07 09:54:35 +01:00
Tim Newsome 21e06e1d89 Fix 32-bit build.
Code taken from http://openocd.zylin.com/#/c/4178/
2017-07-06 14:53:28 -07:00
Tim Newsome 31e5b53a46 Merge pull request from riscv/build32
Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
Tim Newsome 321619946b Merge pull request from riscv/old_triggers
Add back support for type 1 triggers
2017-07-03 13:52:16 -07:00
Palmer Dabbelt 3cff4213a4 Merge pull request from riscv/multi-gdb
Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
Tim Newsome 450307b66f Fix 32-bit build errors.
I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes .
2017-07-03 12:17:07 -07:00
Tim Newsome f18fd83ac7 Fix trigger set/clear bug. 2017-07-03 11:52:35 -07:00
Tim Newsome 6c627e9ea9 Add back support for type 1 triggers.
They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
2017-07-03 11:01:10 -07:00
Dmitry Ryzhov 99a3673507 Fix comment about saving the temporary register in examine procedure. 2017-07-01 15:09:23 +03:00
Steven Stallion 0e4fbfba03 rtos: better sanity checking for uCOS-III
This patch improves the OSRunning check. If the rtos_running check
fails, update_threads will return an error rather than attempt to update
the thread list using bad values.

Change-Id: I8614c325504d3a9ab19aebb6862b1fe445a0c8e7
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4166
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-06-30 21:23:47 +01:00
Steven Stallion e6fe4dddb9 rtos: style corrections for uCOS-III
This patch corrects a number of style infractions in RTOS support for
uC/OS-III. These were missed during initial review last year prior to
the 0.10.0 release.

Change-Id: Ia2139f6ca381d4087fd8ee989f7a03ac474d7440
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4120
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-06-30 21:23:15 +01:00
Dmitry Ryzhov 7d451e00f5 Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction. 2017-06-30 19:15:58 +03:00
Richard Watts b3cf9a665c flash/nor/efm32: Support EZR32HG devices.
Recognise the family number for Silicon Labs EZR32HG devices and
select the correct flash page size.

Change-Id: I876e930f3a9f679557fa0d0acac33e9bbfb28c46
Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
Reviewed-on: http://openocd.zylin.com/3934
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-30 10:57:20 +01:00
Andreas Fritiofson 868a100143 target: Fix snprintf format string and argument mismatch in md output
Commit 47b8cf842 changed the fixed type of the value argument to snprint
but didn't change the format string to match for sizes != 64 bit.

Change-Id: I908b06f49ab69d04224282949190a0de883048e0
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4167
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Philipp Guehring <pg@futureware.at>
2017-06-30 10:06:32 +01:00
Tim Newsome b6f8efbf44 Check for errors in read_csr().
Also slightly improve debugging output.
2017-06-27 15:11:06 -07:00
Palmer Dabbelt d77c4a953c Don't set breakpoints on disabled harts 2017-06-21 12:25:20 -07:00
Palmer Dabbelt 689d0fcaf6 No longer hard-code the non-RTOS hart to 0
I was just being lazy here.
2017-06-21 12:25:19 -07:00
Palmer Dabbelt 4bdb042224 Allow memory writes to proceed on all harts 2017-06-21 12:25:19 -07:00
Palmer Dabbelt a277416a39 Refactor examine, to avoid some assertions
Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart.  Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
Palmer Dabbelt 788908fcf0 Factor out checking if harts should be used
Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled".  This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
Palmer Dabbelt 9f4cac5a38 Set current_hartid from coreid
This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
Tim Newsome 9cd98058a0 Set hardware triggers on all harts.
Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
Tim Newsome 10518351bb Don't immediately segfault with -rtos on v0.11. 2017-06-20 11:32:42 -07:00
Tim Newsome ccdd26e3ef Comment curious code. 2017-06-20 11:32:42 -07:00
Tim Newsome 927f9d8873 Update list of "threads" when harts are discovered.
This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
Tim Newsome 4d264b3579 Put early DEBUG notice of XLEN back. 2017-06-19 08:46:02 -07:00
Marc Schink 1725abc3c0 flash/nor/tcl: Make read_bank parameters optional
Make 'offset' and 'length' parameters optional, if both are omitted
simply read the whole flash bank.

Additionally, check if the 'offset' and 'length' arguments are out of
bounds of the flash bank.

Change-Id: Ib9c1b0538a2c78ebcf702e2da11468dff407f8ff
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3862
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-06-17 12:45:56 +01:00
Marc Schink 7112e5f57a flash/nor/tcl: Respect flash bank boundary in write_bank
Respect the flash bank boundary and write only to the remaining part of
the bank even if the file content is larger.

Change-Id: I8f4c1b161c103a77bdb30c6bf052293b5ed48c41
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3861
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-06-17 12:45:11 +01:00
Marc Schink bdc71c5252 flash/nor/tcl: Make write_bank parameter optional
Make the 'offset' parameter optional, if omitted simply start at the
beginning of the flash bank.

Additionally, check if the argument is out of bounds of the flash bank.

Change-Id: I8e9632b539ad9e83211e1ac6a06da4c8109cbc60
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3860
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-06-17 12:44:25 +01:00
Marc Schink 2de82d39a2 flash/nor/tcl: Respect flash bank boundary in verify_bank
Respect the flash bank boundary and compare only the remaining content
of the bank even if the file content is larger.

Change-Id: I4d75979c7893fdd4d18372fa6b0321a0486b4fa9
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3859
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-06-17 12:43:29 +01:00
Joakim Nohlgård 2c8602ed9f flash Kinetis: Add support for newer KW series
Add support for flashing newer members of the NXP Kinetis KW family

Supported devices:
 - KW20Z
 - KW30Z
 - KW40Z
 - KW21Z
 - KW31Z
 - KW41Z

The earlier KW2xD and KW01Z devices are already supported by the code
for the older K-series.

Verified working on the FRDM-KW41Z development board.
Tested flashing both via GDB `load` and directly via OpenOCD flash
write commands.

Change-Id: I73eae477127a8b54a33005b3b526b5439450a808
Signed-off-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-on: http://openocd.zylin.com/4104
Tested-by: jenkins
Reviewed-by: Johann Fischer <johann_fischer@posteo.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-06-17 12:02:31 +01:00
Tomas Vanek 8dcb91fb83 flash Kinetis: add KL28 device
This device differs a lot from others in KL series.

Unfortunately the System Integration Module, where device
identification resides, moved to a new address so probe now have
to try both addresses of SIM_SDID.

Introduce a new bank creation option: -sim-base to ensure error free probe.

WDOG32 is slightly different from KE1x and on different address.
System Mode Controler changed layout to word aligned.

Change-Id: I2c9dca0c4ad4228fcc941d6078d15f5e394833ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4059
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 12:02:07 +01:00
Tomas Vanek 5a2608bbbc flash Kinetis: handle all types of watchdog, disable in reset-init
Active watchdog forces reset during armv7m_checksum_memory()
in verify_image command if run just after reset init.

COP watchdog in KL series and WDOG32 in KE1 series
have longer timeout however they need to be disabled too.

The change extends 'kinetis disable_wdog' command to optionally
probe the chip and use appropriate algorithm to disable watchdog.

Setting of cache type is also split from flash_support flags.

Tcl command 'kinetis disable_wdog' is called in reset-init event.

Change-Id: I3191e230f38b679ed74f2a97fe323ef8fb3fe22e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3901
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 12:01:55 +01:00
Tomas Vanek c4d4c32a50 flash Kinetis: implement automatic bank creation based on device probe
Kinetis flash driver services huge number of MCU types. They have
one, two or four flash banks with option of FlexNVM. It would
require ~36 config files just for Kx series, more for KLx, KVx and KE1x.

The change implements alternative approach:
- configuration file creates just one pflash bank (common for all devices)
- when a device is probed, additional pflash or flexnvm banks are created
based on flash layout of the connected MCU
- created banks have names with optional numbering e.g. kx.pflash0 kx.pflash1
kx.flexnvm0 kx.flexnvm1
- the first bank gets renamed if numbering is used

Automatic bank creation is enabled by tcl command 'kinetis create_banks'.

Used solution has a drawback: other banks than pflash0 are not accessible
until pflash0 is probed. Fortunately gdb attach and standard programming
accesses banks in right sequence.

Change-Id: I5b9037cbefdb8a4176b7715fbcc3af4da4c1ab60
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3925
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 12:01:45 +01:00
Tomas Vanek 1fdc62ef65 flash Kinetis: split kinetis_chip from kinetis_flash_bank
Kinetis flash driver probed and decoded chip repeatedly for each flash
bank. Bank ordering used global bank number so multi-target
configuration was broken.

The change introduces kinetis_probe_chip() which reads SIM SDID
and SIM FCFG registers, decodes Kinetis series and family
and fills struct kinetis_chip. This probe runs once for all banks.

struct kinetis_chip contains pointers to all flash banks embeded
in the MCU. It simplifies iteration over all or specific MCU banks.

kinetis_probe_chip() generates MCU name and some informational messages
are improved.

Change-Id: I990db5c63ba490667eec0e5459086d83936662fb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3924
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 12:01:24 +01:00
Tomas Vanek 16f364a591 flash Kinetis: add KV5x family
Real time control MCU has a Cortex-M7 and numerous changes in flash layout.
Introduced a new ID of MDM-AP.

While on it a LOG_DEBUG format error fixed.

Change-Id: I1018660ce0c3dd63ac5e2563408fabff3c3daef7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3900
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 12:01:04 +01:00
Tomas Vanek 97d296637e flash Kinetis: add KL8x family, fix erase check
Secure devices KL81Z7 and KL82Z7 have no SERIESID field in ID register
so they have to be decoded in Kx branch (not KLx).

The flash controller in KL8x and also in K8x devices does not implement
FTFx_CMD_BLOCKSTAT command. Fix kinetis_blank_check() to work properly
using FTFx_CMD_SECTSTAT command only.
Introduce a new flag FS_NO_CMD_BLOCKSTAT to avoid use of FTFx_CMD_BLOCKSTAT
on these devices.

Change-Id: I3ff58718480acd8cce69f618f71667b6b1d9c4f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3898
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 12:00:53 +01:00
Tomas Vanek a0a504569b flash Kinetis: add KE1xZ and KE1xF families
The new Kinetis KE1x families use FTFE flash controller unlike KE0x.
Also SDID coding corresponds to new K, KL and KV families.
That's why KE1x is handled by kinetis driver instead of kinetis_ke

Change-Id: Ibb73e28e41dfbb086e761e1f006b089825dab854
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3896
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 11:59:36 +01:00
Tomas Vanek 278f63174d flash/nor: at91samd modified to use real erase sector size
Before this change SAMD driver defined "sector" equal to a flash
protection block. Oversize sectors (16kB for the biggest flash size)
made problems for flashing firmware split to two or more parts.

Removed superfluous test of sector protection before erase.

Change-Id: I8e6a6bda6ccd91eda2df67ec48270c69faa1bdd1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3546
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 11:58:26 +01:00
Tomas Vanek 24c302752e flash/nor/at91sam4: remove FWS=6, rename at91samg to atsamg
FWS=6 workaround removed, as this appears to be a copy-paste error
from the SAM3X family. Originally addressed in http://openocd.zylin.com/3837
but not all occurences were removed.

Atmel changed chip naming and removed 91 prefix for atsamg, samd...

Change-Id: Ia2b43da82b2ff9b1c85fdb456a0a198ab095243d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3926
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-17 11:56:54 +01:00
Tim Newsome 6082f35a55 Update debug_defines. Clarify debug output.
Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
Tim Newsome fd81f7fcac Fix comment. 2017-06-16 14:02:25 -07:00
Tim Newsome 851849a295 Tell the user about detected harts. 2017-06-16 14:02:25 -07:00
Tim Newsome 3abb347bd9 Tighten up debug output.
Assuming the program allocating code works, we don't need its output.
Only output parts of the debug RAM that are actually doing something.
2017-06-16 14:02:25 -07:00
Tim Newsome ac2da40f74 Fix indentation to match OpenOCD style.
This change is just in the whitespace. There are no code changes.

See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
Tim Newsome 363a0a2bf2 Merge pull request from riscv/release-fixes
Two fixes from the release branch
2017-06-15 12:43:46 -07:00
Tim Newsome 50a223ef9a Fix print statements to work with 64-bit addresses 2017-06-15 12:24:37 -07:00
Palmer Dabbelt afc9eb6c47 Jump to the RTOS hartid after halting
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting.  This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
2017-06-15 12:16:33 -07:00
Palmer Dabbelt 099a3020d2 Clear abstract errors from register_read_direct 2017-06-15 12:16:24 -07:00
Tim Newsome 503da094e8 Accept 64-bit addresses in CRC requests. 2017-06-15 10:44:37 -07:00
Tim Newsome 64af052911 Fix the build.
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
Tim Newsome 845c2f6b69 Merge branch 'remotes/openocd/master' into riscv64
Merged 1025be363e

Conflicts:
	src/flash/nor/Makefile.am
	src/rtos/Makefile.am
	src/rtos/rtos.c
	src/target/Makefile.am
	src/target/target.c
	src/target/target_type.h

Doesn't build yet, but I fixed the conflicts that git pointed out.
2017-06-13 11:52:50 -07:00
Tim Newsome 6be600318c Fix dmi_read() indentation; remove \n in LOG_ERROR 2017-06-08 12:31:08 -07:00
Megan Wachs c3b344d1c0 riscv: Move the initialization of the field inside the structure for consistency 2017-06-07 21:06:33 -07:00
Megan Wachs 459b39ec67 riscv: v13 -- dmi_write must still check for the OP result 2017-06-07 21:06:33 -07:00
Tim Newsome 11008baee3 %p already includes 0x (on gcc) 2017-06-06 11:51:15 -07:00
Tim Newsome 83afb93004 Don't leave fd undefined.
When gcc isn't optimizing well, it might not realize that it's not
possible to return fd without initializing it, and then the build fails
due to -Werror.
2017-06-06 11:51:15 -07:00
Paul Fertser 1025be363e flash: nor: ath79: fix build failure due to recent MIPS changes
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4151
Tested-by: jenkins
Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
2017-06-02 20:20:26 +01:00
Tobias Diedrich 6b9d19d367 flash: Add support for Atheros (ath79) SPI interface
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558

Extended and revised version of my original patch submitted by Dmytro
here: http://openocd.zylin.com/#/c/3390

This driver is using pure SPI mode, so the flash base address is not
used except some flash commands (e.g. "flash program") need it to
distinguish the banks.

Example config with all 3 chip selects:
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2

Example usage:
> flash probe flash0
Found flash device 'win w25q128fv' (ID 0x001840ef)
flash 'ath79' found at 0x00000000
> flash probe flash1
No SPI flash found
> flash probe flash2
No SPI flash found
> flash banks
> flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
reading 4096 bytes from flash @0x00000000
wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
0x00000000 in 28.688066s (0.139 KiB/s)

Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: http://openocd.zylin.com/3612
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-31 08:18:29 +01:00
Grzegorz Kostka 83c67b7ac7 imx_gpio: add mmap based jtag interface for IMX processors
For some targets (like nrf51) sysfs driver is too slow. This
patch implements memory maped driver for IMX processors.
Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should
work on any NXP IMX CPU.

Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7
Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-on: http://openocd.zylin.com/4106
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-31 08:16:17 +01:00
Palmer Dabbelt 51ab5a0c8b Return 5 (SIGBREAK) not 2 (SIGINT) after a step
GDB seems to just go off the rails if I return a SIGINT.
2017-05-25 18:31:58 -07:00
Palmer Dabbelt f0969e7c71 Pass EVENT_RESUMED in the RTOS
I missed this event.  It appears to do nothing.
2017-05-25 13:14:31 -07:00
Palmer Dabbelt ab77c5d792 Invalidate the register cache when rtos_hartid==-1
This means I don't know what hart to look at, so I might as well
invalidate the register cache.  Without this, you might get stale
registers the first time you ask for them.
2017-05-25 13:14:31 -07:00
Palmer Dabbelt faa6123e36 Invalidate the register cache on step, resume, reset
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode.  With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
2017-05-25 13:14:31 -07:00
Megan Wachs e12f5575ef riscv-v11: Don't perform unexpected operation in cache_write 2017-05-22 22:02:01 -07:00
Palmer Dabbelt c431c0eb25 Check for abstractcs.busy, not just CMDERR_BUSY
This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
Palmer Dabbelt a8cf04b839 Go back to 32-word read/write buffers
The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
Palmer Dabbelt e31761df64 Don't re-read registers after they're written
This was just a sanity check.
2017-05-15 16:57:08 -07:00
Palmer Dabbelt 9d308db2bc Print out the actual CSR that's read 2017-05-15 16:56:50 -07:00
Palmer Dabbelt 8252b9d36c Build fixes 2017-05-15 13:39:58 -07:00
Megan Wachs af6e04d5c0 riscv: Remove some compile warnings 2017-05-15 13:36:05 -07:00
Forest Crossman f6449a7cba jtag/drivers: Add Cypress KitProg driver
This patch adds a driver for the SWD-only Cypress KitProg
programmer/debugger.

Change-Id: I3a9a8011a762781d560ebb305597e782a4f9a8e5
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/3221
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-05-12 10:08:43 +01:00