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ethernet
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WIP 100BASE-TX PHY
74 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson f4c2b1eb1f pmd_dp83223: Don't intentionally cause bit errors 
On stretches without transitions, we can lose (or gain) a bit, depending
on how the reciever is reckoning. This can cause spurious test failures
when we get especially unlucky. Keep track of our running disparity
(time-wise, not value-wise) and keep perfect time until we get a
transition (or we start moving back in the right direction).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-30 22:14:18 -04:00
rtl pmd_dp83223: Delay signal_status by an additional clock 2022-10-30 22:02:32 -04:00
tb pmd_dp83223: Don't intentionally cause bit errors 2022-10-30 22:14:18 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00