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pmd_dp83223: Delay signal_status by an additional clock 

When increasing the delay for the recieved data, I forgot to increase
the delay for the signal status as well. Fix this.

Fixes: c02d3f3 ("pmd_io: Calculate wraparound based on state and not state_next")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2022-10-30 22:02:32 -04:00
parent cf0aed4980
commit 63006ca9c0
1 changed files with 3 additions and 3 deletions
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6
rtl/pmd_dp83223_rx.v
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@ -27,7 +27,7 @@ module pmd_dp83223_rx (
);
reg [1:0] rx_p, rx_n;
reg [3:0] sd_delay;
reg [4:0] sd_delay;
`ifdef SYNTHESIS
SB_IO #(
@ -64,9 +64,9 @@ module pmd_dp83223_rx (
* it helps out during simulation. It also helps avoid metastability.
*/
always @(posedge clk_125)
sd_delay[3:1] <= sd_delay[2:0];
sd_delay[4:1] <= sd_delay[3:0];
assign signal_status = sd_delay[3];
assign signal_status = sd_delay[4];
/*
* Get things into the clk_250 domain so that we sample posedge before