From 63006ca9c0af7bbd07e9967cafa6ba32ccd7209b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sun, 30 Oct 2022 22:02:32 -0400 Subject: [PATCH] pmd_dp83223: Delay signal_status by an additional clock When increasing the delay for the recieved data, I forgot to increase the delay for the signal status as well. Fix this. Fixes: c02d3f3 ("pmd_io: Calculate wraparound based on state and not state_next") Signed-off-by: Sean Anderson --- rtl/pmd_dp83223_rx.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/pmd_dp83223_rx.v b/rtl/pmd_dp83223_rx.v index 9d1493d..d3890bf 100644 --- a/rtl/pmd_dp83223_rx.v +++ b/rtl/pmd_dp83223_rx.v @@ -27,7 +27,7 @@ module pmd_dp83223_rx ( ); reg [1:0] rx_p, rx_n; - reg [3:0] sd_delay; + reg [4:0] sd_delay; `ifdef SYNTHESIS SB_IO #( @@ -64,9 +64,9 @@ module pmd_dp83223_rx ( * it helps out during simulation. It also helps avoid metastability. */ always @(posedge clk_125) - sd_delay[3:1] <= sd_delay[2:0]; + sd_delay[4:1] <= sd_delay[3:0]; - assign signal_status = sd_delay[3]; + assign signal_status = sd_delay[4]; /* * Get things into the clk_250 domain so that we sample posedge before