Automatically dump signals

While manually dumping signals with a macro works OK for standalone
modules, it doesn't work when multiple modules are included. Instead,
create a second top-level module to dump signals. Inspired (once again)
by [1].

[1] https://github.com/steveicarus/iverilog/issues/376#issuecomment-709907692
Signed-off-by: Sean Anderson <seanga2@gmail.com>

Makefile

@@ -22,9 +22,7 @@ log:
 	$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $< -l log/$(*F).synth
 
 define run-jsontov =
-	( echo '`include "common.vh"'; grep timescale $*.v; \
-	  $(SYNTH) -q -p "write_verilog -defparam -noattr" -f json $< ) | \
-	  sed 's/endmodule/`DUMP(1)\n\0/g' > $@
+	( grep timescale $*.v; $(SYNTH) -q -p "write_verilog -defparam -noattr" -f json $< ) > $@
 endef
 
 %.synth.v: %.synth.json %.v
@@ -35,28 +33,29 @@ endef
 
 # Don't warn about including the timescale from common.vh
 IFLAGS := -g2012 -gspecify -Wall -Wno-timescale
+EXTRA_V := rtl/iverilog_dump.v
 
 define run-icarus =
-$(ICARUS) $(IFLAGS) -I$(<D) -M$@.pre -s $(TOP) -o $@ $< $(EXTRA_V) && \
+$(ICARUS) $(IFLAGS) -I$(<D) -y$(<D) -M$@.pre -DTOP=$(TOP) -s $(TOP) -s dump -o $@ $< $(EXTRA_V) && \
 	( echo -n "$@: " && tr '\n' ' ' ) < $@.pre > $@.d; RET=$$?; rm -f $@.pre; exit $$RET
 endef
 
 %.vvp: TOP = $(*F)
-%.vvp: %.v
+%.vvp: %.v rtl/iverilog_dump.v
 	$(run-icarus)
 
 %.synth.vvp: TOP = $(*F)
-%.synth.vvp %.place.vvp: EXTRA_V := $(shell $(SYNTH)-config --datdir)/ice40/cells_sim.v
+%.synth.vvp %.place.vvp: EXTRA_V += $(shell $(SYNTH)-config --datdir)/ice40/cells_sim.v
 # Don't warn about unused SB_IO ports
 %.synth.vvp: IFLAGS += -Wno-portbind
-%.synth.vvp: %.synth.v
+%.synth.vvp: %.synth.v rtl/iverilog_dump.v
 	$(run-icarus)
 
 %.place.vvp: TOP = top
 # Don't warn about unused SB_IO ports
 %.place.vvp: IFLAGS += -Wno-portbind
 %.place.vvp: IFLAGS += -DTIMING -Ttyp
-%.place.vvp: %.place.v
+%.place.vvp: %.place.v rtl/iverilog_dump.v
 	$(run-icarus)
 
 %.asc %.sdf %.place.json &: %.synth.json | log
@@ -79,13 +78,15 @@ define run-vvp =
 MODULE=tb.$* $(VVP) $(VVPFLAGS) $< $(PLUSARGS)
 endef
 
+%.fst: PLUSARGS += +levels=0
 %.fst: rtl/%.vvp tb/%.py FORCE
 	$(run-vvp)
 
+%.synth.fst: PLUSARGS += +levels=1
 %.synth.fst: rtl/%.synth.vvp tb/%.py FORCE
 	$(run-vvp)
 
-%.place.fst: PLUSARGS += +sdf=rtl/$*.sdf
+%.place.fst: PLUSARGS += +levels=1 +sdf=rtl/$*.sdf
 %.place.fst: rtl/%.place.vvp rtl/%.sdf tb/%.py FORCE
 	$(run-vvp)
 

rtl/common.vh

@@ -9,19 +9,4 @@
 `default_nettype none
 `timescale 1ns/1ns
 
-`ifdef SYNTHESIS
-`define DUMP(levels)
-`else
-`define DUMP(levels) \
-	reg [4096:0] vcdfile, sdffile; \
-	initial begin \
-		if ($value$plusargs("vcd=%s", vcdfile)) begin \
-			$dumpfile(vcdfile); \
-			$dumpvars(levels); \
-		end \
-		if ($value$plusargs("sdf=%s", sdffile)) \
-			$sdf_annotate(sdffile); \
-	end
-`endif
-
 `endif /* COMMON_VH */

rtl/descramble.v

@@ -115,6 +115,4 @@ module descramble (
 		end
 	end
 
-	`DUMP(0)
-
 endmodule

rtl/iverilog_dump.v

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: AGPL-3.0-Only
+/*
+ * Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
+ */
+
+module iverilog_dump();
+	integer levels;
+	reg [4096:0] vcdfile, sdffile;
+	initial begin
+		if ($value$plusargs("vcd=%s", vcdfile) &&
+		    $value$plusargs("levels=%d", levels)) begin
+			$dumpfile(vcdfile);
+			$dumpvars(levels, `TOP);
+		end
+		if ($value$plusargs("sdf=%s", sdffile))
+			$sdf_annotate(sdffile, `TOP);
+	end
+endmodule

rtl/mdio.v

@@ -216,6 +216,4 @@ module mdio (
 	end
 `endif
 
-	`DUMP(0)
-
 endmodule

rtl/mdio_io.v

@@ -78,6 +78,4 @@ module mdio_io (
 			oe <= 0;
 	end
 
-	`DUMP(0)
-
 endmodule

rtl/mdio_regs.v

@@ -149,6 +149,4 @@ module mdio_regs (
 		data_read <= data_read_next;
 	end
 
-	`DUMP(0)
-
 endmodule

rtl/mii_io_rx.v

@@ -121,6 +121,4 @@ module mii_io_rx (
 	end
 `endif
 
-	`DUMP(0)
-
 endmodule

rtl/mii_io_tx.v

@@ -113,6 +113,4 @@ module mii_io_tx (
 	end
 `endif
 
-	`DUMP(0)
-
 endmodule

rtl/nrzi_decode.v

@@ -34,6 +34,4 @@ module nrzi_decode (
 		nrz <= nrz_next;
 	end
 
-	`DUMP(0)
-
 endmodule

rtl/nrzi_encode.v

@@ -20,6 +20,4 @@ module nrzi_encode (
 	always @(posedge clk)
 		nrzi <= nrzi_next;
 
-	`DUMP(0)
-
 endmodule

rtl/pcs.v

@@ -90,8 +90,6 @@ module pcs (
 	assign col = transmitting && receiving;
 	assign crs = transmitting || receiving;
 
-	`DUMP(0)
-
 endmodule
 
 /* Transmit process */

rtl/pmd_io.v

@@ -213,6 +213,4 @@ module pmd_io (
 	end
 `endif
 
-	`DUMP(0)
-
 endmodule

rtl/scramble.v

@@ -23,6 +23,4 @@ module scramble (
 	always @(posedge clk)
 		lfsr = { lfsr[9:0], lfsr_next };
 
-	`DUMP(0)
-
 endmodule