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WIP 100BASE-TX PHY
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Sean Anderson 3ec1f4d77d Automatically dump signals 
While manually dumping signals with a macro works OK for standalone
modules, it doesn't work when multiple modules are included. Instead,
create a second top-level module to dump signals. Inspired (once again)
by [1].

[1] https://github.com/steveicarus/iverilog/issues/376#issuecomment-709907692
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-30 14:20:48 -04:00
rtl Automatically dump signals 2022-10-30 14:20:48 -04:00
tb pcs: data_?x -> ?x_data 2022-10-16 18:58:29 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00