Sean Anderson ece7d6c619 descramble: Pass through scrambled_valid ... Even when signal_status is low, we should still generate data. This keeps the PCS processes moving along. Signed-off-by: Sean Anderson <seanga2@gmail.com>		2022-11-05 11:54:39 -04:00
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common.vh	Automatically dump signals	2022-10-30 14:20:48 -04:00
descramble.v	descramble: Pass through scrambled_valid	2022-11-05 11:54:39 -04:00
io.vh	Add pmd	2022-08-06 14:02:44 -04:00
iverilog_dump.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
mdio.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
mdio_io.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
mdio_regs.v	mdio_regs: Add register to enable test modes	2022-11-02 17:44:37 -04:00
mii_io_rx.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
mii_io_tx.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
nrzi_decode.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
nrzi_encode.v	Automatically dump signals	2022-10-30 14:20:48 -04:00
pcs.vh	pcs: Split into rx/tx	2022-10-30 21:32:02 -04:00
pcs_rx.v	pcs: Split into rx/tx	2022-10-30 21:32:02 -04:00
pcs_tx.v	pcs: Split into rx/tx	2022-10-30 21:32:02 -04:00
pmd_dp83223_rx.v	pmd_dp83223: Delay signal_status by an additional clock	2022-10-30 22:02:32 -04:00
scramble.v	scrambler: Fix wrone assignment type	2022-11-02 00:16:43 -04:00