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ethernet
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WIP 100BASE-TX PHY
78 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson ece7d6c619 descramble: Pass through scrambled_valid 
Even when signal_status is low, we should still generate data. This
keeps the PCS processes moving along.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-11-05 11:54:39 -04:00
rtl descramble: Pass through scrambled_valid 2022-11-05 11:54:39 -04:00
tb mdio_regs: Add register to enable test modes 2022-11-02 17:44:37 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00