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ethernet
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ethernet/rtl
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Sean Anderson 7d93f91dd3 mdio_regs: Test OUI mapping to PHYID 
The OUI in the PHY ID is "bit-reversed," AKA each byte is bit reversed,
but the overall order is the same. This is a bit more complex than I
initially thought. Fix the mapping, and use a non-zero OUI for testing.

Fixes: d9602b6 ("Add MII management functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2023-03-15 14:11:56 -04:00
..
axis_mii_tx.v axis_mii_tx: Add support for half duplex 2023-01-14 00:08:38 -05:00
axis_replay_buffer.v axis_replay_buffer: Fix slave handshaking 2023-03-05 14:30:27 -05:00
axis_wb_bridge.v axis_wb_bridge: Fix wishbone handshaking 2023-03-05 14:30:05 -05:00
common.vh Automatically dump signals 2022-10-30 14:20:48 -04:00
descramble.v rtl: Document calculation of LFSRs 2023-03-15 13:44:20 -04:00
hub.v hub: Add option to register wishbone bus 2023-03-06 22:11:29 -05:00
hub_core.v hub/phy_core: Export some status signals 2023-02-20 23:34:10 -05:00
io.vh Add pmd 2022-08-06 14:02:44 -04:00
iverilog_dump.v Automatically dump signals 2022-10-30 14:20:48 -04:00
led_blinker.v led_blinker: Decrease blink speed to 15 Hz 2023-03-15 14:06:04 -04:00
mdio.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_io.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_regs.v mdio_regs: Test OUI mapping to PHYID 2023-03-15 14:11:56 -04:00
mii_elastic_buffer.v mii_elastic_buffer: Don't use memory access hack on valid/err 2023-02-18 22:48:36 -05:00
mii_io_rx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mii_io_tx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
nrzi_decode.v nrzi_decode: Add reset input 2022-11-30 18:14:23 -05:00
nrzi_encode.v Automatically dump signals 2022-10-30 14:20:48 -04:00
pcs.vh pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
pcs_tx.v pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
phy_core.v rtl: Document calculation of LFSRs 2023-03-15 13:44:20 -04:00
phy_internal.v Support ENABLE_COUNTERS in hub 2023-03-05 20:47:46 -05:00
pmd_dp83223.v Add DP83223-based PMD 2022-11-30 18:14:23 -05:00
pmd_dp83223_rx.v pmd_dp83223_rx: Don't use SB_IO for signal_detect 2023-02-20 18:39:58 -05:00
reset_sync.v Add reset synchronizer 2023-03-05 16:59:17 -05:00
scramble.v scramble: Fix initial lfsr value 2023-01-09 20:51:59 -05:00
uart_rx.v rtl: Document calculation of LFSRs 2023-03-15 13:44:20 -04:00
uart_tx.v rtl: Document calculation of LFSRs 2023-03-15 13:44:20 -04:00
uart_wb_bridge.v Add UART-WIshbone bridge 2023-03-05 14:59:24 -05:00
wb_mux.v Add wishbone mux 2023-02-18 22:48:36 -05:00
wb_reg.v Add wishbone register 2023-03-06 22:00:41 -05:00