51 lines
797 B
Verilog
51 lines
797 B
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module reset_sync (
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input clk,
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input rst_in,
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output reg rst_out
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);
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wire rst;
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reg rst_last;
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initial rst_last = 1;
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initial rst_out = 1;
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`ifdef SYNTHESIS
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/* Filter out glitches */
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wire [3:0] rst_delay;
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assign rst_delay[0] = rst_in;
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assign rst = &rst_delay;
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genvar i;
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generate for (i = 0; i < 3; i = i + 1) begin
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(* keep *)
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SB_LUT4 #(
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.LUT_INIT(16'hff00)
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) filter (
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.I3(rst_delay[i]),
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.O(rst_delay[i + 1])
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);
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end endgenerate
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`else
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assign rst = rst_in;
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`endif
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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rst_last <= 1;
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rst_out <= 1;
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end else begin
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rst_last <= rst;
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rst_out <= rst_last;
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end
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end
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endmodule
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