82 lines
1.4 KiB
Verilog
82 lines
1.4 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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`include "io.vh"
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module mdio_io (
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input clk,
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input mdc,
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inout mdio,
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output reg mdio_oe,
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input mdo,
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input mdo_valid,
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output reg ce,
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output reg mdi
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);
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wire ce_next;
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reg mdi_next;
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reg [1:0] last_mdc;
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/* Two clock delay to allow the level shifter to reverse direction */
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reg [2:0] oe;
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initial oe = 0;
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`ifdef SYNTHESIS
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_REGISTERED)
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) mdc_pin (
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.PACKAGE_PIN(mdc),
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.INPUT_CLK(clk),
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.D_IN_0(last_mdc[0])
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);
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_REGISTERED | `PIN_OUTPUT_ENABLE | `PIN_INPUT_REGISTERED)
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) mdio_pin (
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.PACKAGE_PIN(mdio),
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.INPUT_CLK(clk),
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.OUTPUT_CLK(clk),
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.OUTPUT_ENABLE(oe[2]),
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.D_OUT_0(mdo),
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.D_IN_0(mdi_next),
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);
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED)
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) mdio_oe_pin (
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.PACKAGE_PIN(mdio_oe),
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.OUTPUT_CLK(clk),
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.D_OUT_0(mdo_valid),
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);
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`else
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reg mdio_next;
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always @(posedge clk) begin
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last_mdc[0] <= mdc;
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mdi_next <= mdio;
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mdio_next <= mdo;
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mdio_oe <= mdo_valid;
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end
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assign mdio = oe[2] ? mdio_next : 1'bZ;
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`endif
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assign ce_next = last_mdc[0] && !last_mdc[1];
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always @(posedge clk) begin
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mdi <= mdi_next;
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last_mdc[1] <= last_mdc[0];
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ce <= ce_next;
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if (mdo_valid)
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oe <= { oe[1:0], mdo_valid };
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else
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oe <= 0;
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end
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endmodule
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