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ethernet
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Sean Anderson 599a2fce17 tb: axis_mii_tx: Simulate a longer reset 
Simulate a reset lasting for at least once clock cycle to ensure our
external interfaces act sane.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2023-03-15 15:51:54 -04:00
..
__init__.py Make testbenches a module 2022-08-21 12:36:28 -04:00
axis_mii_tx.py tb: axis_mii_tx: Simulate a longer reset 2023-03-15 15:51:54 -04:00
axis_replay_buffer.py axis_replay_buffer: Don't say we're ready during reset 2023-03-15 15:36:36 -04:00
axis_wb_bridge.py axis_wb_bridge: Fix AXIS master 2023-03-04 14:32:04 -05:00
descramble.py descrambler: Rename unscrambled* to descrambled* 2022-10-16 18:53:47 -04:00
hub.py hub: Add option to register wishbone bus 2023-03-06 22:11:29 -05:00
hub_core.py tb: hub_core: Remove references to Memory 2023-02-18 22:48:36 -05:00
led_blinker.py Add LED blinker 2023-02-18 22:48:36 -05:00
mdio.py tb: mdio: Export wb_read/write/err 2023-03-01 19:19:31 -05:00
mdio_io.py mdio:io: Don't drive mdio as X in testbench 2022-10-16 17:37:38 -04:00
mdio_regs.py mdio_regs: Test OUI mapping to PHYID 2023-03-15 14:11:56 -04:00
mii_elastic_buffer.py tb: mii_elastic_buffer: Remove unnecessary try/except 2023-03-01 19:19:31 -05:00
mii_io_rx.py mii_io: Add isolation support 2022-08-28 18:43:23 -04:00
mii_io_tx.py mii_io: Add isolation support 2022-08-28 18:43:23 -04:00
nrzi_decode.py tb: Use correct width for Xs 2023-03-05 00:03:18 -05:00
nrzi_encode.py nrzi_encode: Fix test name 2022-11-05 12:37:18 -04:00
pcs.py pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.py tb: pcs_rx: Allow err to be optional 2023-01-09 21:02:35 -05:00
pcs_tx.py Add phy_core 2022-11-05 12:37:18 -04:00
phy_core.py tb: phy_core: Make signal_status more robust 2023-03-05 00:13:13 -05:00
pmd_dp83223.py Add DP83223-based PMD 2022-11-30 18:14:23 -05:00
pmd_dp83223_rx.py pmd: Export check_bits from testbench 2023-01-09 20:38:52 -05:00
reset_sync.py Add reset synchronizer 2023-03-05 16:59:17 -05:00
scramble.py Add phy_core 2022-11-05 12:37:18 -04:00
uart_rx.py uart_rx: Fix incorrect handshaking 2023-03-04 16:43:22 -05:00
uart_tx.py uart_tx: Fix AXIS handshaking 2023-03-05 14:30:07 -05:00
uart_wb_bridge.py Add UART-WIshbone bridge 2023-03-05 14:59:24 -05:00
util.py tb: util: Use RisingEdge for ClockEnable 2023-03-01 19:19:31 -05:00
wb_mux.py Add wishbone mux 2023-02-18 22:48:36 -05:00
wb_reg.py Add wishbone register 2023-03-06 22:00:41 -05:00