152 lines
4.5 KiB
Python
152 lines
4.5 KiB
Python
# SPDX-License-Identifier: AGPL-3.0-Only
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# Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import FallingEdge, Timer
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from cocotb.types import LogicArray
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from .util import BIT
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BMCR = 0
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BMSR = 1
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PHYID1 = 2
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PHYID2 = 3
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EXTSTATUS = 15
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NWCR = 16
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PWCR = 17
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DCR = 18
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FCCR = 19
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SECR = 21
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VCR = 30
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BMCR_RESET = BIT(15)
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BMCR_LOOPBACK = BIT(14)
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BMCR_SPEED_LSB = BIT(13)
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BMCR_PDOWN = BIT(11)
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BMCR_ISOLATE = BIT(10)
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BMCR_DUPLEX = BIT(8)
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BMCR_COLTEST = BIT(7)
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BMCR_SPEED_MSB = BIT(6)
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BMSR_100BASEXFD = BIT(14)
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BMSR_100BASEXHD = BIT(13)
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BMSR_LSTATUS = BIT(2)
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BMSR_EXTCAP = BIT(0)
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VCR_DTEST = BIT(15)
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VCR_LTEST = BIT(14)
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async def wb_xfer(signals, addr, data=None, delay=1):
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await FallingEdge(signals['clk'])
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signals['stb'].value = 1
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signals['addr'].value = addr
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if data is None:
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signals['we'].value = 0
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else:
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signals['we'].value = 1
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signals['data_write'].value = data
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for _ in range(delay + 1):
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await FallingEdge(signals['clk'])
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if signals['ack'].value or signals['err'].value:
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break
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assert signals['ack'].value or signals['err'].value
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signals['stb'].value = 0
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signals['we'].value = LogicArray('X')
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signals['addr'].value = LogicArray('X' * len(signals['addr']))
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signals['data_write'].value = LogicArray('X' * 16)
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if data is None and signals['ack'].value:
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return signals['data_read'].value
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@cocotb.test(timeout_time=2, timeout_unit='us')
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async def test_mdio(regs):
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regs.cyc.value = 1
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regs.stb.value = 0
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regs.link_status.value = 1
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regs.positive_wraparound.value = 0
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regs.negative_wraparound.value = 0
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regs.false_carrier.value = 0
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regs.symbol_error.value = 0
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await Timer(1)
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await cocotb.start(Clock(regs.clk, 8, units='ns').start())
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def xfer(regad, data=None):
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return wb_xfer({
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'clk': regs.clk,
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'stb': regs.stb,
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'we': regs.we,
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'addr': regs.addr,
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'data_write': regs.data_write,
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'data_read': regs.data_read,
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'ack': regs.ack,
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'err': regs.err,
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}, regad, data)
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async def reg_toggle(reg, bit, signal, ro_mask=0):
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if signal:
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assert not signal.value
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await xfer(reg, bit)
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if signal:
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assert signal.value
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assert await xfer(reg) == (ro_mask | bit)
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await xfer(reg, 0)
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if signal:
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assert not signal.value
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def bmcr_toggle(bit, signal):
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return reg_toggle(BMCR, bit, signal, ro_mask=BMCR_SPEED_LSB)
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assert await xfer(BMCR) == (BMCR_SPEED_LSB | BMCR_ISOLATE)
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await bmcr_toggle(BMCR_LOOPBACK, regs.loopback)
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await bmcr_toggle(BMCR_PDOWN, regs.pdown)
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await bmcr_toggle(BMCR_ISOLATE, regs.isolate)
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await bmcr_toggle(BMCR_DUPLEX, None)
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await bmcr_toggle(BMCR_COLTEST, regs.coltest)
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await xfer(BMCR, BMCR_RESET)
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assert await xfer(BMCR) == (BMCR_SPEED_LSB | BMCR_ISOLATE)
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await xfer(BMSR, 0xffff)
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assert await xfer(BMSR) == (BMSR_100BASEXFD | BMSR_100BASEXHD | BMSR_LSTATUS | BMSR_EXTCAP)
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regs.link_status.value = 0
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assert not await xfer(BMSR) & BMSR_LSTATUS
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regs.link_status.value = 1
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assert not await xfer(BMSR) & BMSR_LSTATUS
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assert await xfer(BMSR) & BMSR_LSTATUS
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await xfer(PHYID1, 0xffff)
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assert await xfer(PHYID1) == 0xd5ec
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await xfer(PHYID2, 0xffff)
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assert await xfer(PHYID2) == 0x4800
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# I'm pretty sure this register will never be implemented
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assert await xfer(EXTSTATUS) is None
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assert await xfer(EXTSTATUS, 0) is None
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async def counter_test(reg, signal, edge_triggered=False, active_high=True):
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signal.value = 1 if active_high else 0
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await FallingEdge(regs.clk)
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assert await xfer(reg) == 1
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await xfer(reg, 0xfffe)
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if edge_triggered:
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signal.value = 0 if active_high else 1
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await FallingEdge(regs.clk)
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if edge_triggered:
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signal.value = 1 if active_high else 0
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await FallingEdge(regs.clk)
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signal.value = 0 if active_high else 1
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assert await xfer(reg) == 0x7fff
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assert await xfer(reg) == 0
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await counter_test(NWCR, regs.negative_wraparound)
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await counter_test(PWCR, regs.positive_wraparound)
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await xfer(DCR) # Clear DCR from the BMSR testing
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await counter_test(DCR, regs.link_status, True, False)
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await counter_test(FCCR, regs.false_carrier)
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await counter_test(SECR, regs.symbol_error)
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await reg_toggle(VCR, VCR_DTEST, regs.descrambler_test)
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await reg_toggle(VCR, VCR_LTEST, regs.link_monitor_test)
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