24.6.1 requires that CRS goes high fewer than 4 cycles after TX_EN goes
high. This means we need to assert tx when we enter then START_J state,
not when we actually transmit a /J/. This also has the upside of
simplifying the logic a bit.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Using -O allows grouping job output, which is helpful when output would
otherwise be interleaved (such as when running tests). However, it also
means that there is no tty attached to the job, resulting in cocotb
automatically turning off color. Detect whether we have a tty during the
parsing phase, and force color output if we do. Technically this should
probably take into account the existing value of COCOTB_ANSI_OUTPUT, but
I don't use it normally.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The PMA also has to deal with "recoverd bitstreams" (that is, inputs which
can have 0, 1, or 2 valid bits). Export the core of pcs_send_codes into its
own function, as it is useful for generating these signals.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Since 0153975 ("tb: pcs: Send packet spacing packets immediately"), we
have never allowed pma_data_rx to remain idle. There's no need to supply
a default value.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The PCS state machine is evaluated every cycle, but its outputs are only
registers when the rx_bits module indicates. However, the flush signal
is not registered and is instead combinatorial. Although it's OK to
evaluate the other outputs every cycle, we should only indicate if we
are actually going to change state.
Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
If we get a run of 1s (or 0s) at the start of the stream, it may take a
while for us to align. Increase the alignment range. Additionally, from
testing, it appears that negative ranges are never used. Just start at
0.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
In the recieve tests, the harness often has a choice of how fast to feed
data to the module. Up to this point, we have always used the same
strategy (typically random), even when multiple strategies were used
when writing the test. Add parametrization to test different strategies
in each test run. The timing decorator is taken from the cocotb source,
since we can't pass parameters to cocotb.test directly any more.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds support for running testbenches post-synethesis. Simulating
this way should (hopefully) catch most synthesis/simulation mismatches.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a levels parameter to DUMP, allowing dumping just the
top-level signals, instead of the whole hierarchy. This is helpful for
post-synthesis simulation, where all sub-modules are primitives (with
their inputs and outputs already available at the top level).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a helper for printing input/output serial data. Early errors
might not have had the offending bits printed, since slicing
doesn't work with negative indices.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
valid is an internal signal which isn't available in post-synthesis
simulation. Use signal_status instead, which is externally available.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We set this signal for debugging purposes, so don't die if it's absent
(such as in a post-synthesis simulation).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
To make sure that pmd.signal_status comes up at the right time, keep
signal_detect low at the start of simulation. We don't need to set
pmd.rx, because X is the default value (or rather Z is, but it's the
same for our purposes).
Fixes: 1d65661 ("Add pmd")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The data yielded by the PMD is not really valid until it has made its
way through the pipeline. Delay it until the data is valid. As a side
effect, this should also eliminate any metastability. This is not
necessary for real hardware, but it allows us to to post-synthesis
simulation (where we can't reach in and probe the internal valid
signal).
Additionally, ensure that the state is known by resetting it when we
don't have a signal.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Ensure all inputs are initialized before starting the clocks. This
avoids any problems which might occur due to everything being
initialized at once.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Instead of calculating clock periods based on the desired frequncy,
specify the periods diretly. This silences the following kind of error
caused by floating point rounding:
Unable to accurately represent 8000.000000000001(sec) with the simulator precision of 1e-12
Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
There were two unused variables; remove them. The wrong type of
assignments were used; fix them.
Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Without this state, receiving would immediately go low. However, figure
24-11 shows that receiving should go low only after an additional code
group (the second idle) is received.
Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
When the PMA has no new data for us, idle should be determined based on
raw_bits[11:2]. However, we just calculated that last cycle, so we can
reuse it.
Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
There's no strict requirement for us to handle linke failures immediately.
The PMA's link timer will ensure the signal stays low, so we don't have to
worry about missing it. This fixes some strange Xs during initialization.
Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson