Move default_nettype/timescale declaration to common.vh

We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Makefile

@@ -17,10 +17,11 @@ FORCE:
 	$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $<
 
 %.post.v: %.json %.v
-	( grep timescale $*.v && echo '`include "common.vh"' && \
+	( echo '`include "common.vh"'; grep timescale $*.v; \
 	  $(SYNTH) -q -b verilog -f json $< ) | sed 's/endmodule/`DUMP(1)\n\0/g' > $@
 
-IFLAGS := -g2012 -Wall
+# Don't warn about including the timescale from common.vh
+IFLAGS := -g2012 -Wall -Wno-timescale
 
 define run-icarus =
 $(ICARUS) $(IFLAGS) -I$(<D) -M$@.pre -s $(TOP) -o $@ $< $(EXTRA_V) && \

rtl/common.vh

@@ -6,6 +6,9 @@
 `ifndef COMMON_VH
 `define COMMON_VH
 
+`default_nettype none
+`timescale 1ns/1ns
+
 `ifdef SYNTHESIS
 `define DUMP(levels)
 `else

rtl/pcs.v

@@ -3,8 +3,6 @@
  * Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
  */
 
-`default_nettype none
-
 `include "common.vh"
 
 /* 4b5b code groups */