WIP 100BASE-TX PHY

Sean Anderson 897326dbdb Move default_nettype/timescale declaration to common.vh ... We will need this in every verilog file, so consolidate things a bit. In terms of timescale, we need to modify the post-synthesis verilog generation a bit in order to avoid the module's timecale being inadverdently overwritten. Signed-off-by: Sean Anderson <seanga2@gmail.com>		2022-08-24 12:04:10 -04:00
rtl	Move default_nettype/timescale declaration to common.vh	2022-08-24 12:04:10 -04:00
tb	Make testbenches a module	2022-08-21 12:36:28 -04:00
.gitignore	Ignore post-synthesis verilog	2022-08-21 12:36:36 -04:00
4b5b.gtkw	Initial commit	2022-05-23 20:57:03 -04:00
Makefile	Move default_nettype/timescale declaration to common.vh	2022-08-24 12:04:10 -04:00