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ethernet/Makefile

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Initial commit
2022-05-15 21:52:26 -05:00
# SPDX-License-Identifier: AGPL-3.0-Only
# Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
Q = 1
SYNTH = yosys
PNR = nextpnr-ice40
ICARUS = iverilog
VVP = vvp
.PHONY: all
all: rtl/pcs.asc
.PHONY: FORCE
FORCE:
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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%.synth.json: %.v
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $<
Initial commit
2022-05-15 21:52:26 -05:00
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
2022-09-04 16:14:45 -05:00
%.synth.v: %.synth.json %.v
Move default_nettype/timescale declaration to common.vh We will need this in every verilog file, so consolidate things a bit. In terms of timescale, we need to modify the post-synthesis verilog generation a bit in order to avoid the module's timecale being inadverdently overwritten. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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( echo '`include "common.vh"'; grep timescale $*.v; \
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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$(SYNTH) -q -b verilog -f json $< ) | sed 's/endmodule/`DUMP(1)\n\0/g' > $@
Move default_nettype/timescale declaration to common.vh We will need this in every verilog file, so consolidate things a bit. In terms of timescale, we need to modify the post-synthesis verilog generation a bit in order to avoid the module's timecale being inadverdently overwritten. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-21 11:41:19 -05:00
# Don't warn about including the timescale from common.vh
IFLAGS := -g2012 -Wall -Wno-timescale
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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define run-icarus =
$(ICARUS) $(IFLAGS) -I$(<D) -M$@.pre -s $(TOP) -o $@ $< $(EXTRA_V) && \
( echo -n "$@: " && tr '\n' ' ' ) < $@.pre > $@.d; RET=$$?; rm -f $@.pre; exit $$RET
endef
%.vvp: TOP = $(*F)
Initial commit
2022-05-15 21:52:26 -05:00
%.vvp: %.v
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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$(run-icarus)
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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%.synth.vvp: TOP = $(*F)
%.synth.vvp: EXTRA_V := $(shell $(SYNTH)-config --datdir)/ice40/cells_sim.v
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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# Don't warn about unused SB_IO ports
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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%.synth.vvp: IFLAGS += -Wno-portbind
%.synth.vvp: %.synth.v
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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$(run-icarus)
Initial commit
2022-05-15 21:52:26 -05:00
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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%.asc: %.synth.json
Initial commit
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$(PNR) --pcf-allow-unconstrained --freq 125 --hx8k --package ct256 --json $< --asc $@
-include $(wildcard rtl/*.d)
export LIBPYTHON_LOC := $(shell cocotb-config --libpython)
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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VVPFLAGS := -M $(shell cocotb-config --lib-dir)
VVPFLAGS += -m $(shell cocotb-config --lib-name vpi icarus)
Support colorized output with -O Using -O allows grouping job output, which is helpful when output would otherwise be interleaved (such as when running tests). However, it also means that there is no tty attached to the job, resulting in cocotb automatically turning off color. Detect whether we have a tty during the parsing phase, and force color output if we do. Technically this should probably take into account the existing value of COCOTB_ANSI_OUTPUT, but I don't use it normally. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 11:07:25 -05:00
# Always use color output if we have a tty. This allows for easy use of -O
ifeq ($(shell test -c /dev/stdin && echo 1),1)
export COCOTB_ANSI_OUTPUT=1
endif
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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define run-vvp =
MODULE=tb.$* $(VVP) $(VVPFLAGS) $< -fst +vcd=$@
endef
Initial commit
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%.fst: rtl/%.vvp tb/%.py FORCE
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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$(run-vvp)
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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%.synth.fst: rtl/%.synth.vvp tb/%.py FORCE
Add post-synthesis simulation support This adds support for running testbenches post-synethesis. Simulating this way should (hopefully) catch most synthesis/simulation mismatches. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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$(run-vvp)
Initial commit
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Rename pmd to pmd_io This better reflects the function of the module (interfacing the transciever via the I/O pins), and fits better with the naming scheme used for other I/O modules. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-28 16:25:24 -05:00
MODULES := pcs pmd_io nrzi_encode nrzi_decode scramble descramble mdio mdio_io mii_io_rx mii_io_tx
Add MII management functions This adds a module implementing the the MII management functions (the MDIO regs). For the moment, we just implement the standard registers. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-29 20:37:10 -05:00
MODULES += mdio_regs
Use MODULE variable for tests Instead of listing out tested modules each time, use a variable. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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Initial commit
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.PHONY: test
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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test: $(addsuffix .fst,$(MODULES)) $(addsuffix .synth.fst,$(MODULES))
Initial commit
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.PHONY: clean
clean:
rm *.fst
Rename *post* targets to *synth* The post here originally stood for post-synthesis. To add support for post-placement simulation and reduce ambiguity, rename these targets to *synth*.
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cd rtl && rm -f *.json *.asc *.pre *.vvp *.d *.synth.v