Commit Graph

14 Commits

Author SHA1 Message Date
Sean Anderson 42c1e93338 Rename *post* targets to *synth*
The post here originally stood for post-synthesis. To add support for
post-placement simulation and reduce ambiguity, rename these targets to
*synth*.
2022-09-04 17:14:45 -04:00
Sean Anderson d9602b6f78 Add MII management functions
This adds a module implementing the the MII management functions (the
MDIO regs). For the moment, we just implement the standard registers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-31 12:36:11 -04:00
Sean Anderson ead545e85e Rename pmd to pmd_io
This better reflects the function of the module (interfacing the
transciever via the I/O pins), and fits better with the naming scheme
used for other I/O modules.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-28 17:25:24 -04:00
Sean Anderson 0c2989b13c Add MII input transmit interface
The actitecture is overall fairly similar to the receive interface,
except that the directions are mostly different. The timing is a bit
easier, since we control the ce signal. Data is sampled one clock before
tx_clk goes high, which is the earliest that it is guarantee'd to be
valid. We could get an extra half-clock by having tx_clk go high at the
negedge of clk, but it's unnecessary at the moment.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-28 17:16:33 -04:00
Sean Anderson e2544d702f Add MII output receive interface
This generates the appropriate output for MII receive signals. Because
we don't have a clock synchronous to the recieved data, we may
occasionally have some cycles which are 32 ns or 48 ns long (instead of
the nominal 40 ns). This distorts the duty cycle to 38% or 58%,
respectively, which is within the specified 35% to 65%. This does change
the frequency to either 31 MHz or 21 MHz, respectively, which *is* a
violation of the spec. This could be avoided by introducing a FIFO to
smooth out any variations in jitter, like what RMII does.

The generation of rx_clk is a bit tricky. We can use a combinatorial
signal for the posedge, since that is what the rest of the logic is
referenced to, However, we need to register the negedge to prevent an
early (or late) ce from modifying the duty cycle.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-28 17:09:51 -04:00
Sean Anderson dd4183991d Add MDIO I/O module
This module implements the I/O portion of the MII management interface.
The output is delayed by 2 clocks in order to ensure that the external
level shifter has switched directions before we drive it. The latency
increase (around 16 ns) is not consequential, since we have around 300
ns from the rising edge of MDC before MDIO has to be valid.

On the other end, the timing requirements for MDIO driven by the STA are
very lenient (for them); MDIO only has to be valid for 10 ns on either
side of the rising edge of MDC. This effectively means we must sample
MDIO synchronously to MDC (not easy with nextpnr), or oversample by 50x.
Fortunately, we have a 125 MHz clock which the rest of the phty runs off
of. However, this basically makes 10x oversampling with the MII clock
impossible.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-28 12:21:02 -04:00
Sean Anderson f1b345299e Add mdio module
This module implements the MII management interface ("MDIO"), and
translates frames into classic wishbone reads/writes. We use a
"state_counter" to keep track of how many additional bits we expect to
recieve before continuing on to the next field in the frame. We require
a preamble because it prevents ambiguity, and omitting it doesn't seem
to be very popular (seeing as it was removed for c45). Generally, even
if we find an error in the frame, we still procede through the states as
usual. This prevents any spurious reads/writes caused by misinterpreting
an unaligned data stream.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-27 15:59:29 -04:00
Sean Anderson 12a4678442 Add (de)scrambling support
This adds support for (de)scrambling as described in X3.263. The
scrambler is fairly straightforward. Because we only have to recognize
idles, and because the timing constraints are more relaxed (than e.g.
the PCS), we can make several simplifications not found in other
designs (e.g. X3.263 Annex G or DP83222).

First, we can reuse the same register for the lfsr as for the input
ciphertext. This is because we only need to record the scrambled data
when we are unlocked, and we can easily recover the unscrambled data
just by an inversion (as opposed to needing to align with /H/ etc).

Second, it is not critical what the exact thresholds are for locking an
unlocking, as long as certain minimums are met. This allows us to ignore
edge cases, such as if we have data=10 and valid=2. Without these
relaxed constraints, we would need to special-case this input to ensure
we didn't miss the last necessary consecutive idle. But instead we just
set the threshold such that one missed bit does not matter.

To support easier testing, a test input may be used to cause the
descramble to become unlocked after only 5us, instead of the mandated
361. This makes simulation go much faster.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-27 13:06:38 -04:00
Sean Anderson c6f95ce26f Add NRZI support
This adds support for encoding and decoding nrzi data.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:29:09 -04:00
Sean Anderson 86aee33477 Use MODULE variable for tests
Instead of listing out tested modules each time, use a variable.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:10:07 -04:00
Sean Anderson 50c1080ba4 Support colorized output with -O
Using -O allows grouping job output, which is helpful when output would
otherwise be interleaved (such as when running tests). However, it also
means that there is no tty attached to the job, resulting in cocotb
automatically turning off color. Detect whether we have a tty during the
parsing phase, and force color output if we do. Technically this should
probably take into account the existing value of COCOTB_ANSI_OUTPUT, but
I don't use it normally.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:07:25 -04:00
Sean Anderson 897326dbdb Move default_nettype/timescale declaration to common.vh
We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:04:10 -04:00
Sean Anderson 6ffb3481fe Add post-synthesis simulation support
This adds support for running testbenches post-synethesis. Simulating
this way should (hopefully) catch most synthesis/simulation mismatches.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson d351291ff8 Initial commit 2022-05-23 20:57:03 -04:00