Add mdio module
This module implements the MII management interface ("MDIO"), and
translates frames into classic wishbone reads/writes. We use a
"state_counter" to keep track of how many additional bits we expect to
recieve before continuing on to the next field in the frame. We require
a preamble because it prevents ambiguity, and omitting it doesn't seem
to be very popular (seeing as it was removed for c45). Generally, even
if we find an error in the frame, we still procede through the states as
usual. This prevents any spurious reads/writes caused by misinterpreting
an unaligned data stream.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson
parent
4646500973
commit
f1b345299e
2
Makefile
2
Makefile
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@ -63,7 +63,7 @@ endef
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%.post.fst: rtl/%.post.vvp tb/%.py FORCE
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$(run-vvp)
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MODULES := pcs pmd nrzi_encode nrzi_decode scramble descramble
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MODULES := pcs pmd nrzi_encode nrzi_decode scramble descramble mdio
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.PHONY: test
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test: $(addsuffix .fst,$(MODULES)) $(addsuffix .post.fst,$(MODULES))
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@ -0,0 +1,214 @@
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// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module mdio (
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input clk,
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input ce,
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input mdi,
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output reg mdo,
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output reg mdo_valid,
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input ack,
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output cyc,
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output reg stb, we,
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output reg [4:0] addr,
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output reg [15:0] data_write,
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input [15:0] data_read
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);
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parameter [PHYAD_BITS-1:0] ADDRESS = 0;
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localparam IDLE = 0;
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localparam PREAMBLE = 1;
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localparam ST = 2;
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localparam OP = 3;
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localparam PHYAD = 4;
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localparam REGAD = 5;
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localparam TA = 6;
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localparam DATA = 7;
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localparam PREAMBLE_BITS = 32;
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localparam OP_BITS = 2;
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localparam PHYAD_BITS = 5;
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localparam REGAD_BITS = 5;
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localparam TA_BITS = 2;
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localparam DATA_BITS = 16;
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localparam OP_READ = 2'b10;
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localparam OP_WRITE = 2'b01;
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reg mdo_next, mdo_valid_next;
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reg stb_next, we_next;
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initial stb = 0;
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reg [4:0] addr_next;
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reg [15:0] data_next;
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reg bad, bad_next;
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reg [2:0] state = IDLE, state_next;
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reg [4:0] state_counter, state_counter_next;
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/*
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* NB: stb_next and data_next are assigned to stb and data_write every
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* clock, whereas the other signals are only assigned if ce is high.
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* This ensures that no duplicate reads/writes are issued, and that
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* data_read is sampled promptly. However, it also means that any
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* assignments to these regs in the state machine must be qualified
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* by ce.
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*/
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always @(*) begin
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mdo_next = 1'bX;
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mdo_valid_next = 0;
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stb_next = stb;
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we_next = we;
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addr_next = addr;
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data_next = data_write;
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if (stb && ack) begin
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stb_next = 0;
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data_next = data_read;
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end
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state_next = state;
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state_counter_next = state_counter - 1;
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bad_next = bad;
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case (state)
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IDLE: begin
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bad_next = 0;
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state_counter_next = PREAMBLE_BITS - 1;
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if (mdi)
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state_next = PREAMBLE;
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end
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PREAMBLE: begin
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if (!state_counter)
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state_counter_next = 0;
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if (!mdi) begin
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if (state_counter)
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state_next = IDLE;
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else
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state_next = ST;
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end
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end
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ST: begin
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if (!mdi)
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bad_next = 1;
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state_next = OP;
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state_counter_next = OP_BITS - 1;
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end
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OP: begin
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/* This is a bit of an abuse of we :) */
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we_next = mdi;
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if (!state_counter) begin
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case ({ we, mdi })
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OP_READ: we_next = 0;
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OP_WRITE: we_next = 1;
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default: bad_next = 1;
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endcase
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state_next = PHYAD;
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state_counter_next = PHYAD_BITS - 1;
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end
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end
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PHYAD: begin
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if (mdi != ADDRESS[state_counter])
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bad_next = 1;
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if (!state_counter) begin
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/* Cancel any outstanding transaction */
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if (ce)
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stb_next = 0;
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state_next = REGAD;
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state_counter_next = REGAD_BITS - 1;
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end
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end
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REGAD: begin
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addr_next = { addr[3:0], mdi };
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if (!state_counter) begin
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if (ce && !we && !bad)
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stb_next = 1;
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state_next = TA;
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state_counter_next = TA_BITS - 1;
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end
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end
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TA: begin
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if (!state_counter) begin
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if (!we && !bad) begin
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mdo_next = 0;
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mdo_valid_next = 1;
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if (stb) begin
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/* No response */
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stb_next = !ce;
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bad_next = 1;
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mdo_valid_next = 0;
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end
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end
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state_next = DATA;
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state_counter_next = DATA_BITS - 1;
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end
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end
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DATA: begin
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if (ce && we) begin
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data_next = { data_write[14:0], mdi };
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end else if (!bad) begin
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/* More data_write abuse */
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mdo_next = data_write[15];
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mdo_valid_next = 1;
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if (ce)
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data_next = { data_write[14:0], 1'bX };
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end
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if (!state_counter) begin
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if (ce && we && !bad)
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stb_next = 1;
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bad_next = 0;
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state_next = IDLE;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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stb <= stb_next;
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data_write <= data_next;
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if (ce) begin
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mdo <= mdo_next;
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mdo_valid <= mdo_valid_next;
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we <= we_next;
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addr <= addr_next;
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state <= state_next;
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state_counter <= state_counter_next;
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bad <= bad_next;
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end
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end
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/* No multi-beat transactions */
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assign cyc = stb;
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`ifndef SYNTHESIS
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reg [255:0] state_text;
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always @(*) begin
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case (state)
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IDLE: state_text = "IDLE";
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PREAMBLE: state_text = "PREAMBLE";
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ST: state_text = "ST";
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OP: state_text = "OP";
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PHYAD: state_text = "PHYAD";
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REGAD: state_text = "REGAD";
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TA: state_text = "TA";
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DATA: state_text = "DATA";
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endcase
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end
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`endif
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`DUMP(0)
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endmodule
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@ -0,0 +1,169 @@
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# SPDX-License-Identifier: AGPL-3.0-Only
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# Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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import random
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import ClockCycles, Edge, FallingEdge, First, RisingEdge, Timer
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from cocotb.types import LogicArray
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from .util import ClockEnable
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def to_bits(val, width):
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for bit in range(width - 1, -1, -1):
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yield (val >> bit) & 1
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def frame(phyad, regad, data=None, *, st=0b01, op=None, preamble_bits=32):
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for _ in range(preamble_bits):
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yield 1
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yield from to_bits(st, 2)
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if op is None:
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op = 0b10 if data is None else 0b01
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yield from to_bits(op, 2)
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yield from to_bits(phyad, 5)
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yield from to_bits(regad, 5)
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if data is None:
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return
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yield 1
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yield 0
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yield from to_bits(data, 16)
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# Should be 50, but reduced to simulate faster
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MDIO_RATIO = 3
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async def mdio_read(mdio, phyad, regad, **kwargs):
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ret = 0
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for bit in frame(phyad, regad, **kwargs):
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await RisingEdge(mdio.ce)
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mdio.mdi.value = bit
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await FallingEdge(mdio.ce)
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mdio.mdi.value = LogicArray('X')
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for bit in range(19):
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await RisingEdge(mdio.ce)
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await RisingEdge(mdio.clk)
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if bit < 2:
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continue
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if bit == 2:
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if not mdio.mdo_valid.value:
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ret = None
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continue
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if ret is None:
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assert not mdio.mdo_valid.value
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continue
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else:
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assert mdio.mdo_valid.value
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ret <<= 1
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ret |= mdio.mdo.value
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return ret
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async def mdio_write(mdio, phyad, regad, data, **kwargs):
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for bit in frame(phyad, regad, data, **kwargs):
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await RisingEdge(mdio.ce)
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mdio.mdi.value = bit
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await FallingEdge(mdio.ce)
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mdio.mdi.value = LogicArray('X')
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async def wb_read(mdio, addr, data):
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while not (mdio.cyc.value and mdio.stb.value):
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await FallingEdge(mdio.clk)
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assert not mdio.we.value
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assert mdio.addr.value == addr
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mdio.data_read.value = data
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mdio.ack.value = 1
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await RisingEdge(mdio.clk)
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mdio.ack.value = 0
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mdio.data_read.value = LogicArray('X' * 16)
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await FallingEdge(mdio.clk)
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assert not mdio.stb.value
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async def wb_write(mdio, addr, data):
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while not (mdio.cyc.value and mdio.stb.value):
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await FallingEdge(mdio.clk)
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mdio.ack.value = 1
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await RisingEdge(mdio.clk)
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assert mdio.we.value
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assert mdio.addr.value == addr
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assert mdio.data_write.value == data
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mdio.ack.value = 0
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await FallingEdge(mdio.clk)
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assert not mdio.stb.value
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async def setup(mdio):
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mdio.mdi.value = 0
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mdio.ack.value = 0
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mdio.data_read.value = LogicArray('X' * 16)
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await cocotb.start(ClockEnable(mdio.clk, mdio.ce, MDIO_RATIO))
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await Timer(1)
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await cocotb.start(Clock(mdio.clk, 8, units='ns').start())
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@cocotb.test(timeout_time=50, timeout_unit='us')
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async def test_mdio(mdio):
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await setup(mdio)
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reads = [(i, random.randrange(0, 0xFFFF)) for i in range(16)]
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writes = [(i, random.randrange(0, 0xFFFF)) for i in range(16)]
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random.shuffle(reads)
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random.shuffle(writes)
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async def rw_mdio():
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for (read, write) in zip(reads, writes):
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assert await mdio_read(mdio, 0, read[0]) == read[1]
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await mdio_write(mdio, 0, write[0], write[1])
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await cocotb.start(rw_mdio())
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for (read, write) in zip(reads, writes):
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await wb_read(mdio, read[0], read[1])
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await wb_write(mdio, write[0], write[1])
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@cocotb.test(timeout_time=20, timeout_unit='us')
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async def test_badmdio(mdio):
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await setup(mdio)
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async def nowb():
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await First(RisingEdge(mdio.cyc), RisingEdge(mdio.stb))
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assert False, "Unexpected wishbone transaction"
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await cocotb.start(nowb())
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# Force mdi low to ensure we get exactly 31 bits in the preamble
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async def rw_mdio(phyad, **kwargs):
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mdio.mdi.value = 0
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await FallingEdge(mdio.clk)
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assert await mdio_read(mdio, phyad, 0, **kwargs) is None
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mdio.mdi.value = 0
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await FallingEdge(mdio.clk)
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await mdio_write(mdio, phyad, 0, 0, **kwargs)
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await rw_mdio(0, preamble_bits=31)
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await rw_mdio(0, st=0b00)
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await rw_mdio(0, op=0b00)
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await rw_mdio(1)
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await rw_mdio(0x10)
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@cocotb.test(timeout_time=20, timeout_unit='us')
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async def test_badwb(mdio):
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await setup(mdio)
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async def try_mdio():
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assert await mdio_read(mdio, 0, 0) is None
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await mdio_write(mdio, 0, 0, 0)
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assert await mdio_read(mdio, 0, 0) is None
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await cocotb.start(try_mdio())
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await ClockCycles(mdio.stb, 3, False)
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