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ethernet
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WIP 100BASE-TX PHY
59 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 2832c79ff0 pmd_io: Switch to single-ended tx signal 
The singal-ended to differential conversion will be done by the
transceiver (by the ECL interface circuit).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-16 17:42:17 -04:00
rtl pmd_io: Switch to single-ended tx signal 2022-10-16 17:42:17 -04:00
tb mdio:io: Don't drive mdio as X in testbench 2022-10-16 17:37:38 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Rename *post* targets to *synth* 2022-09-04 17:14:45 -04:00